公开(公告)号：US20060231899A1

公开(公告)日：2006-10-19

申请号：US11108012

申请日：2005-04-15

申请人： Leland Chang ,  Shreesh Narasimha ,  Norman Rohrer ,  Jeffrey Sleight

发明人： Leland Chang ,  Shreesh Narasimha ,  Norman Rohrer ,  Jeffrey Sleight

IPC分类号： H01L29/94

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

摘要翻译： 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：US20080096330A1

公开(公告)日：2008-04-24

申请号：US11958877

申请日：2007-12-18

申请人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

发明人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L21/84

CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

公开(公告)号：US20050287823A1

公开(公告)日：2005-12-29

申请号：US10710257

申请日：2004-06-29

申请人： Ravikumar Ramachandran ,  James Kelliher ,  Shreesh Narasimha ,  Jeffrey Sleight

发明人： Ravikumar Ramachandran ,  James Kelliher ,  Shreesh Narasimha ,  Jeffrey Sleight

IPC分类号： H01L21/31 ,  H01L21/318 ,  H01L21/44 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/823864

摘要： A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%-15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.

摘要翻译： 用于形成PFET器件的氮化硅间隔物材料和用于制造间隔物的方法包括使用双频等离子体增强CVD工艺，其中温度在通过低温下沉积氮化硅层的范围 双频等离子体增强CVD工艺，温度范围为400°C至550°C。工艺压力范围为2 Torr至5 Torr。 低频功率在0W至50W的范围内，高频功率在90W至110W的范围内。硅烷，氨和氮气的前体气体以240：3200：4000的比例流动 sccm。 与具有通过RTCVD工艺形成的氮化硅间隔物的类似PFET器件相比，使用本发明的氮化硅间隔物形成具有双间隔物的PFET器件导致10％-15％的性能提高。

公开(公告)号：US20050236687A1

公开(公告)日：2005-10-27

申请号：US10830347

申请日：2004-04-22

申请人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

发明人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US20090315138A1

公开(公告)日：2009-12-24

申请号：US12141276

申请日：2008-06-18

申请人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L27/12 ,  H01L21/3205

CPC分类号： H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.

摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。

公开(公告)号：US07804140B2

公开(公告)日：2010-09-28

申请号：US12041967

申请日：2008-03-04

申请人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L27/088

CPC分类号： H01L29/4238 ,  H01L29/7833

摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.

摘要翻译： 沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。 可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。 可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。 由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。

公开(公告)号：US20090072312A1

公开(公告)日：2009-03-19

申请号：US11855204

申请日：2007-09-14

申请人： Leland Chang ,  Shreesh Narasimha ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Shreesh Narasimha ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/665 ,  H01L29/66545

摘要： A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack.

摘要翻译： 混合取向技术（HOT）CMOS结构由拉伸应力NFET栅极堆叠和压缩应力PFET栅极堆叠构成，其中每个栅极堆叠由高介电常数氧化物/金属组成，并且其中源 拉伸应力NFET栅极堆叠和压应力PFET栅极堆叠是高k金属栅极堆叠中的金属。

公开(公告)号：US07274072B2

公开(公告)日：2007-09-25

申请号：US11108012

申请日：2005-04-15

申请人： Leland Chang ,  Shreesh Narasimha ,  Norman J. Rohrer ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Shreesh Narasimha ,  Norman J. Rohrer ,  Jeffrey W. Sleight

IPC分类号： H01L29/72

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

摘要翻译： 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

公开(公告)号：US07893494B2

公开(公告)日：2011-02-22

申请号：US12141276

申请日：2008-06-18

申请人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.

摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。

公开(公告)号：US20090224335A1

公开(公告)日：2009-09-10

申请号：US12041967

申请日：2008-03-04

申请人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L29/7833

摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.

摘要翻译： 沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。 可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。 可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。 由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。