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公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译： 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间，将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。
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公开(公告)号：US20130223121A1
公开(公告)日：2013-08-29
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译： 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间，将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。
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3.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权需要单极编程的双极型二极管三维存储器的解码方案公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。
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4.发明申请DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING 有权用于双极二极管的三维存储器的解码方案需要单核编程公开(公告)号：US20140022850A1
公开(公告)日：2014-01-23
申请号：US13551597
申请日：2012-07-17
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 该系统包括电耦合到多个列电压的列电压开关。 列电压开关包括电耦合到双向存取二极管的输出。 多个列电压包括至少一个选择列电压和一个取消选择列电压。 该系统包括电耦合到多个行电压的行电压开关。 行电压开关包括电耦合到双向存取二极管的输出。 多个行电压包括至少一个选择行电压和一个取消选择行电压。 该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。
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公开(公告)号：US08943374B2
公开(公告)日：2015-01-27
申请号：US13551728
申请日：2012-07-18
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C15/046 , G11C29/32 , G11C29/44
摘要： A system for programming a phase change material-content addressable memory (PCM-CAM). The system includes a receiving unit for receiving a word to be written in the PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The system includes a writing unit configured to repeatedly write the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and to write high bits in memory cells of the PCM-CAM only once.
摘要翻译： 用于编程相变材料内容可寻址存储器（PCM-CAM）的系统。 该系统包括用于接收要写入PCM-CAM中的单词的接收单元。 该字包括由PCM-CAM中的低电阻状态表示的低位和由PCM-CAM中的高电阻状态表示的高位。 该系统包括：写入单元，被配置为重复写入PCM-CAM的存储单元中的低位，直到存储器单元的电阻低于阈值，并且仅在PCM-CAM的存储器单元中写入高位一次。
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公开(公告)号：US20140092694A1
公开(公告)日：2014-04-03
申请号：US13584120
申请日：2012-10-28
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/06 , G11C2207/068
摘要： An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.
摘要翻译： 示例性实施例是用于确定存储器单元的二进制值的电路。 该电路包括具有不同电容的并联电容器以选择性地与存储器单元耦合;以及控制器，被配置为将并联电容器迭代地充电至第一电压，直到所选择的并联电容器使第一电压衰减通过存储器单元为第一参考电压 在预定时间范围内，基于所选择的并联电容器确定存储器单元的最高有效位的二进制值，在确定存储器单元的最高有效位的二进制值之后，将所选择的并联电容器充电至第二电压， 并且基于通过存储器单元的所选择的并联电容器处的第二电压的衰减来确定存储器单元的最低有效位的二进制值。
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7.发明申请DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING 有权用于双极二极管的三维存储器的解码方案需要单核编程公开(公告)号：US20140022851A1
公开(公告)日：2014-01-23
申请号：US13584423
申请日：2012-08-13
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。
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公开(公告)号：US08560902B1
公开(公告)日：2013-10-15
申请号：US13587146
申请日：2012-08-16
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C15/046 , G11C29/32 , G11C29/44
摘要： A method for programming a Phase Change Material-Content Addressable Memory (PCM-CAM). The method includes receiving a word to be written in a PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The method further includes repeatedly writing the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and writing the high bits in memory cells of the PCM-CAM only once.
摘要翻译： 一种用于编程相变材料内容可寻址存储器（PCM-CAM）的方法。 该方法包括接收要写入PCM-CAM的单词。 该字包括由PCM-CAM中的低电阻状态表示的低位和由PCM-CAM中的高电阻状态表示的高位。 该方法还包括在PCM-CAM的存储单元中重复写低位，直到存储单元的电阻低于阈值，并将PCM-CAM的存储单元中的高位写入一次。
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9.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权需要单极编程的双极型二极管三维存储器的解码方案公开(公告)号：US08842491B2
公开(公告)日：2014-09-23
申请号：US13551597
申请日：2012-07-17
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 该系统包括电耦合到多个列电压的列电压开关。 列电压开关包括电耦合到双向存取二极管的输出。 多个列电压包括至少一个选择列电压和一个取消选择列电压。 该系统包括电耦合到多个行电压的行电压开关。 行电压开关包括电耦合到双向存取二极管的输出。 多个行电压包括至少一个选择行电压和一个取消选择行电压。 该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。
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公开(公告)号：US08837198B2
公开(公告)日：2014-09-16
申请号：US13584120
申请日：2012-10-28
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
CPC分类号： G11C7/00 , G11C7/06 , G11C2207/068
摘要： An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.
摘要翻译： 示例性实施例是用于确定存储器单元的二进制值的电路。 该电路包括具有不同电容的并联电容器以选择性地与存储器单元耦合;以及控制器，被配置为将并联电容器迭代地充电至第一电压，直到所选择的并联电容器使第一电压衰减通过存储器单元为第一参考电压 在预定时间范围内，基于所选择的并联电容器确定存储器单元的最高有效位的二进制值，在确定存储器单元的最高有效位的二进制值之后，将所选择的并联电容器充电至第二电压， 并且基于通过存储器单元的所选择的并联电容器处的第二电压的衰减来确定存储器单元的最低有效位的二进制值。
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