-
1.发明授权Switching a defective signal line with a spare signal line without shutting down the computer system 失效在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线公开(公告)号：US07793143B2
公开(公告)日：2010-09-07
申请号：US12098294
申请日：2008-04-04
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译： 一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。 服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。 如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号相关联的驱动器/接收器对中的开关控制单元 线路，以便在从存储器控制器开关控制单元接收到命令时能够用备用线路切换有缺陷的信号线。 以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。
-
2.发明授权Switching a defective signal line with a spare signal line without shutting down the computer system 失效在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线公开(公告)号：US07380161B2
公开(公告)日：2008-05-27
申请号：US11056886
申请日：2005-02-11
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译： 一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。 服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。 如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。 服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。 以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。
-
3.发明申请SWITCHING A DEFECTIVE SIGNAL LINE WITH A SPARE SIGNAL LINE WITHOUT SHUTTING DOWN THE COMPUTER SYSTEM 失效切换带有备用信号线的有缺陷的信号线，而不需要切断计算机系统公开(公告)号：US20080215929A1
公开(公告)日：2008-09-04
申请号：US12098294
申请日：2008-04-04
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译： 一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。 服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。 如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。 服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。 以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。
-
公开(公告)号：US07571357B2
公开(公告)日：2009-08-04
申请号：US11466111
申请日：2006-08-22
IPC分类号： G06F11/00
CPC分类号： G01R31/31722 , G01R31/31712 , G11C29/48
摘要： A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.
摘要翻译： 用于处理单元的存储器控制器提供存储器包裹测试模式路径，其选择性地将数据从控制器的写入缓冲器写入到控制器的读取缓冲器，从而允许写入和读取缓冲器在测试期间替换系统存储器件 处理单元。 因此，处理单元可以在没有附加的存储器件的情况下进行测试，但仍然在产生与实际（最终使用）操作下生成的总线流量和芯片噪声类似的条件下操作。 当处理器在测试模式下发出写入操作时，控制器将数据写入对应于写入地址的读取缓冲器的条目。 此后，处理器可以发出具有相同地址的读取操作，并且读取缓冲器将从相应的条目发送数据。
-
公开(公告)号：US20080126911A1
公开(公告)日：2008-05-29
申请号：US11466111
申请日：2006-08-22
IPC分类号： G11C29/00
CPC分类号： G01R31/31722 , G01R31/31712 , G11C29/48
摘要： A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.
摘要翻译： 用于处理单元的存储器控制器提供存储器包裹测试模式路径，其选择性地将数据从控制器的写入缓冲器写入到控制器的读取缓冲器，从而允许写入和读取缓冲器在测试期间替换系统存储器件 处理单元。 因此，处理单元可以在没有附加的存储器件的情况下进行测试，但仍然在产生与实际（最终使用）操作下生成的总线流量和芯片噪声类似的条件下操作。 当处理器在测试模式下发出写入操作时，控制器将数据写入对应于写入地址的读取缓冲器的条目。 此后，处理器可以发出具有相同地址的读取操作，并且读取缓冲器将从相应的条目发送数据。
-
6.发明授权公开(公告)号：US08930776B2
公开(公告)日：2015-01-06
申请号：US13598072
申请日：2012-08-29
IPC分类号： G06F11/00
CPC分类号： G11C29/023 , G06F11/073 , G06F11/0793 , G06F13/1689 , G11C11/40 , G11C29/028 , G11C29/44
摘要： A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.
摘要翻译： 提供了一种用于实现命令定时调整以减轻计算机系统中的动态随机存取存储器（DRAM）故障的方法，系统和计算机程序产品。 检测到预定义的DRAM故障。 响应于检测到的故障，调整一组定时器以控制用于访问DRAM的预定定时。 响应于通过调整的定时器组来解决故障，执行预定的性能水平的检查。
-
7.发明授权Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module 有权在DRAM模块中选择性地提供使用用于DRAM修复的数据寄存器来实现增强的硬件辅助DRAM修复公开(公告)号：US09063902B2
公开(公告)日：2015-06-23
申请号：US13343938
申请日：2012-01-05
CPC分类号： G06F11/1666 , G06F11/1048 , G06F11/141 , G06F11/20 , G11C29/76
摘要： A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.
摘要翻译： 提供了一种在支持ECC的计算机系统中实现硬件辅助动态随机存取存储器（DRAM）修复的方法，系统和计算机程序产品。 提供DRAM修复的数据寄存器被选择性地提供在动态随机存取存储器（DRAM），存储器控制器或耦合在DRAM和存储器控制器之间的存储缓冲器之一中。 数据寄存器被配置为映射到任何地址。 响应于所检测到的配置地址，从配置的地址的读取或写入路由到数据寄存器。
-
8.发明申请公开(公告)号：US20140068322A1
公开(公告)日：2014-03-06
申请号：US13598072
申请日：2012-08-29
IPC分类号： G06F11/14
CPC分类号： G11C29/023 , G06F11/073 , G06F11/0793 , G06F13/1689 , G11C11/40 , G11C29/028 , G11C29/44
摘要： A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.
摘要翻译： 提供了一种用于实现命令定时调整以减轻计算机系统中的动态随机存取存储器（DRAM）故障的方法，系统和计算机程序产品。 检测到预定义的DRAM故障。 响应于检测到的故障，调整一组定时器以控制用于访问DRAM的预定定时。 响应于通过调整的定时器组来解决故障，执行预定的性能水平的检查。
-
公开(公告)号：US20140063987A1
公开(公告)日：2014-03-06
申请号：US13597926
申请日：2012-08-29
IPC分类号： G11C7/00
CPC分类号： G11C29/04 , G06F13/1673 , G11C29/70 , G11C29/808 , G11C2029/0411
摘要： A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.
-
10.发明申请公开(公告)号：US20130138901A1
公开(公告)日：2013-05-30
申请号：US13307149
申请日：2011-11-30
申请人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Anil B. Lingambudi , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Anil B. Lingambudi , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/16
CPC分类号： G06F11/3037 , G06F11/1658 , G06F11/1666 , G06F11/3058 , G06F2201/81
摘要： A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.
摘要翻译： 一种方法，系统和计算机程序产品实现了对系统热条件的计算机系统的存储器性能管理和增强的存储器可靠性。 当主存储器温度达到初始温度阈值时，读取将暂停到主存储器，并将读取提供给镜像存储器对中的镜像存储器，并将写入提供给主存储器和镜像存储器。 如果主存储器温度达到第二温度阈值，则对主存储器的写操作也被停止，并且主存储器通过诸如自定时刷新（STR）的DRAM省电模式被关闭，并且读取和写入被限制为 在镜像存储器对中镜像存储器。 当初级存储器温度降低到低于初始温度阈值时，通过将相干拷贝从镜像存储器写入主存储器来恢复一致性。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.022 秒)
