公开(公告)号：US20110215873A1

公开(公告)日：2011-09-08

申请号：US12715749

申请日：2010-03-02

申请人： Leo Montreuil ,  Larry Stephen McKinney ,  Jiening Ao ,  Joel Paul Jenkins

发明人： Leo Montreuil ,  Larry Stephen McKinney ,  Jiening Ao ,  Joel Paul Jenkins

IPC分类号： H03L7/00

CPC分类号： H03L7/00 ,  Y10S331/02

摘要： Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

摘要翻译： 本发明的一些实施例可以包括包括固件的DPLL电路。 固件可以包括能够接收参考时钟定时信号和VCXO时钟定时信号的重新采样的NCO相位检测器。 重新采样的NCO相位检测器可以包括能够接收相位输出和VCXO时钟定时信号并重新采样相位输出的重采样器; 以及减法器，其能够从所计算的相位输出的平均值接收所述重采样相位输出并减去所述重采样相位输出。 固件还可以包括能够接收参考时钟定时信号和VCXO时钟定时信号的频率检测器; 以及能够根据频率锁定状态在重新采样的NCO相位检测器和频率检测器之间切换的多路复用器。

公开(公告)号：US20080022338A1

公开(公告)日：2008-01-24

申请号：US11427742

申请日：2006-06-29

申请人： Leo Montreuil ,  Wayne B. Williams ,  Samuel H. Russ ,  Robert A. Kriete

发明人： Leo Montreuil ,  Wayne B. Williams ,  Samuel H. Russ ,  Robert A. Kriete

IPC分类号： H04N7/173 ,  H04N7/16

CPC分类号： H04N17/004 ,  H04N17/04

摘要： Included are systems and methods for testing functionality of a set top terminal (STT). At least one embodiment of a method includes retrieving a test pattern from a storage device, the test pattern being configured to facilitate testing of at least one component of the STT, decoding the retrieved test pattern, and converting the decoded test pattern to at least one analog signal.

摘要翻译： 包括用于测试机顶终端（STT）功能的系统和方法。 方法的至少一个实施例包括从存储设备检索测试模式，测试模式被配置为便于测试STT的至少一个组件，解码所检索的测试模式，以及将解码的测试模式转换成至少一个 模拟信号。

公开(公告)号：US5960044A

公开(公告)日：1999-09-28

申请号：US749025

申请日：1996-11-14

申请人： Leo Montreuil

发明人： Leo Montreuil

IPC分类号： H03D3/00 ,  H04L27/00 ,  H04L27/227 ,  H04L27/233 ,  H04L27/38 ,  H03D1/24

CPC分类号： H04L27/2332 ,  H03D3/006 ,  H03D3/007 ,  H04L2027/003 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

摘要： A block phase estimator include a phase averaging circuit. A first embodiment of the phase averaging circuit includes a phase differencing circuit coupled to an averager input, a first modulo circuit coupled to the phase differencing circuit, a filter coupled to the first modulo circuit, and a summation circuit having an positive input and a negative input, the positive input being coupled to the averager input, the negative input being coupled to the filter. The phase averaging circuit further includes a second modulo circuit coupled to the summation circuit. An alternative embodiment of the phase averaging circuit includes a delay line having a plurality of taps coupled to an averager input and a plurality of first subtractor circuits, a first input of each first subtractor circuit being coupled to the averager input, a second input of each first subtractor circuit being coupled to a corresponding tap of the plurality of taps. A plurality of first modulo circuits are coupled to the plurality of first subtractor circuits, each first modulo circuit being coupled to a corresponding first subtractor circuit. A summation circuit is coupled to all first modulo circuits, and a scaling circuit is coupled to the summation circuit. The phase averaging circuit further includes a second subtractor circuit, a first input of the second subtractor circuit being coupled to the averager input, a second input of the second subtractor circuit being coupled to the scaling circuit.

摘要翻译： 块相位估计器包括相位平均电路。 相位平均电路的第一实施例包括耦合到平均器输入的相位差分电路，耦合到相位差电路的第一模数电路，耦合到第一模数电路的滤波器以及具有正输入和负的总和电路 输入，正输入耦合到平均器输入，负输入耦合到滤波器。 相位平均电路还包括耦合到求和电路的第二模数电路。 相位平均电路的替代实施例包括具有耦合到平均器输入的多个抽头和多个第一减法器电路的延迟线，每个第一减法器电路的第一输入耦合到平均器输入，每个第二输入 第一减法器电路耦合到多个抽头的对应抽头。 多个第一模数电路耦合到多个第一减法器电路，每个第一模数电路耦合到对应的第一减法器电路。 求和电路耦合到所有第一模数电路，并且缩放电路耦合到求和电路。 相位平均电路还包括第二减法器电路，第二减法器电路的第一输入端耦合到平均器输入端，第二减法器电路的第二输入端耦合到缩放电路。

公开(公告)号：US08286067B2

公开(公告)日：2012-10-09

申请号：US12581740

申请日：2009-10-19

申请人： Vladimir Friedman ,  Reza Alavi ,  Raju Hormis ,  Leo Montreuil

发明人： Vladimir Friedman ,  Reza Alavi ,  Raju Hormis ,  Leo Montreuil

IPC分类号： G06F11/10

CPC分类号： H04L12/2838 ,  H03M13/093 ,  H04L1/0057 ,  H04L2012/2849

摘要： A method for delivering control information together with sampled data between a DSP and an RF/analog front-end in a high speed communication modem, which embeds sampled data and control information in frames to be transferred over one interface. A frame may comprise various fields, each may consist of one or more bytes or octets. The frame may have a data field for carrying the sampled data, and at least one control field for transferring the control information to update RF/analog front-end registers. The control field may include an octet containing a control address, an octet containing a control command, and an octet containing control data. The frame may also provide means of synchronization, e.g., by using a sync field to identify the frame boundary.

摘要翻译： 一种用于在高速通信调制解调器中的DSP和RF /模拟前端之间传送控制信息以及采样数据的方法，该方法将采样数据和控制信息嵌入到要通过一个接口传送的帧中。 帧可以包括各种字段，每个字段可以由一个或多个字节或八位字节组成。 帧可以具有用于承载采样数据的数据字段，以及用于传送控制信息以更新RF /模拟前端寄存器的至少一个控制字段。 控制字段可以包括包含控制地址的八位字节，包含控制命令的八位字节和包含控制数据的八位位组。 该帧还可以提供同步的方式，例如通过使用同步字段来识别帧边界。

公开(公告)号：US20100199158A1

公开(公告)日：2010-08-05

申请号：US12581740

申请日：2009-10-19

申请人： Vladimir Friedman ,  Reza Alavi ,  Raju Hormis ,  Leo Montreuil

发明人： Vladimir Friedman ,  Reza Alavi ,  Raju Hormis ,  Leo Montreuil

IPC分类号： H04B1/38 ,  H03M13/09 ,  G06F11/10

CPC分类号： H04L12/2838 ,  H03M13/093 ,  H04L1/0057 ,  H04L2012/2849

摘要： A method for delivering control information together with sampled data between a DSP and an RF/analog front-end in a high speed communication modem, which embeds sampled data and control information in frames to be transferred over one interface. A frame may comprise various fields, each may consist of one or more bytes or octets. The frame may have a data field for carrying the sampled data, and at least one control field for transferring the control information to update RF/analog front-end registers. The control field may include an octet containing a control address, an octet containing a control command, and an octet containing control data. The frame may also provide means of synchronization, e.g., by using a sync field to identify the frame boundary.

摘要翻译： 一种用于在高速通信调制解调器中的DSP和RF /模拟前端之间传送控制信息以及采样数据的方法，该方法将采样数据和控制信息嵌入到要通过一个接口传送的帧中。 帧可以包括各种字段，每个字段可以由一个或多个字节或八位字节组成。 帧可以具有用于承载采样数据的数据字段，以及用于传送控制信息以更新RF /模拟前端寄存器的至少一个控制字段。 控制字段可以包括包含控制地址的八位字节，包含控制命令的八位字节和包含控制数据的八位位组。 该帧还可以提供同步的方式，例如通过使用同步字段来识别帧边界。

公开(公告)号：US07499822B2

公开(公告)日：2009-03-03

申请号：US11427745

申请日：2006-06-29

申请人： Leo Montreuil ,  Wayne B. Williams ,  Samuel H. Russ ,  Robert A. Kriete

发明人： Leo Montreuil ,  Wayne B. Williams ,  Samuel H. Russ ,  Robert A. Kriete

IPC分类号： G06F3/02

CPC分类号： H04N17/004 ,  H04N17/045

摘要： Included are systems and methods for performing a functionality test to an STT. At least one embodiment of a method includes storing at least one test pattern in a storage device, decoding the at least one stored test pattern, and sending the test pattern from a output port to an input port, the input port being coupled to at least one tuning device. Other embodiments include tuning, via the at least one tuning device, the STT according to the test pattern and converting the decoded test pattern to at least one output signal.

摘要翻译： 包括用于对STT执行功能测试的系统和方法。 方法的至少一个实施例包括将至少一个测试模式存储在存储设备中，解码至少一个存储的测试模式，以及将测试模式从输出端口发送到输入端口，该输入端口至少耦合到 一个调谐装置 其他实施例包括经由至少一个调谐装置根据测试图案调整STT，并将解码的测试图案转换成至少一个输出信号。

公开(公告)号：US20080004830A1

公开(公告)日：2008-01-03

申请号：US11427745

申请日：2006-06-29

申请人： Leo Montreuil ,  Wayne B. Williams ,  Samuel H. Russ ,  Robert A. Kriete

发明人： Leo Montreuil ,  Wayne B. Williams ,  Samuel H. Russ ,  Robert A. Kriete

IPC分类号： G06F19/00

CPC分类号： H04N17/004 ,  H04N17/045

摘要： Included are systems and methods for performing a functionality test to an STT. At least one embodiment of a method includes storing at least one test pattern in a storage device, decoding the at least one stored test pattern, and sending the test pattern from a output port to an input port, the input port being coupled to at least one tuning device. Other embodiments include tuning, via the at least one tuning device, the STT according to the test pattern and converting the decoded test pattern to at least one output signal.

摘要翻译： 包括用于对STT执行功能测试的系统和方法。 方法的至少一个实施例包括将至少一个测试模式存储在存储设备中，解码至少一个存储的测试模式，以及将测试模式从输出端口发送到输入端口，该输入端口至少耦合到 一个调谐装置 其他实施例包括经由至少一个调谐装置根据测试图案调整STT，并将解码的测试图案转换成至少一个输出信号。

公开(公告)号：US20130114480A1

公开(公告)日：2013-05-09

申请号：US13288177

申请日：2011-11-03

申请人： John T. Chapman ,  Alon Bernstein ,  Leo Montreuil

发明人： John T. Chapman ,  Alon Bernstein ,  Leo Montreuil

IPC分类号： H04L5/14 ,  H04B1/44

CPC分类号： H04L5/1469 ,  H04H20/79 ,  H04L5/0007 ,  H04N21/2221 ,  H04N21/2408 ,  H04N21/42676 ,  H04N21/6168 ,  H04N21/64322

摘要： A time domain duplex cable system includes a mechanism to change the communication direction of spectrum used in a cable plant including a Cable Modem Termination System (CMTS), a Fiber Node and a plurality of cable modems in communication with the CMTS via the Fiber Node. Active devices, e.g., directional amplifiers switch the communication direction of the cable plant in response to timing information received from the CMTS. To avoid collisions of downstream and upstream packets, a guard time is determined and used in connection with generating the timing information. In one embodiment, the timing information is transmitted in one or more Data Over Cable Service Interface Specifications (DOCSIS) Media Access Protocol (MAP) messages transmitted by the CMTS towards the cable modems.

摘要翻译： 时域双工电缆系统包括用于改变电缆设备中使用的频谱的通信方向的机制，该电缆设备包括通过光纤节点与CMTS通信的电缆调制解调器终端系统（CMTS），光纤节点和多个电缆调制解调器。 有源设备，例如定向放大器，响应于从CMTS接收的定时信息，切换电缆设备的通信方向。 为了避免下游和上游分组的冲突，确定保护时间并且与生成定时信息一起使用。 在一个实施例中，定时信息在由CMTS向电缆调制解调器发送的一个或多个数据有线服务接口规范（DOCSIS）媒体接入协议（MAP）消息中发送。

公开(公告)号：US5477199A

公开(公告)日：1995-12-19

申请号：US319694

申请日：1994-10-07

申请人： Leo Montreuil

发明人： Leo Montreuil

IPC分类号： H04N5/455 ,  H03C3/04 ,  H03C3/40 ,  H03D1/22 ,  H03D1/24 ,  H03D3/00 ,  H03D3/24 ,  H04L27/00 ,  H04L27/02 ,  H04L27/06 ,  H04L27/38 ,  H04N5/44 ,  H03C1/60 ,  H04L27/36

CPC分类号： H03C3/40 ,  H03D1/2254 ,  H04L27/0008 ,  H04L27/02 ,  H04L27/38 ,  H04L27/3836 ,  H04N5/4401 ,  H03C3/04 ,  H03D1/2245 ,  H03D2200/0031 ,  H03D3/007 ,  H03D3/245

摘要： A synchronous detector for demodulating and decoding a digital data signal modulated either according to a vestigial sideband or a quadrature amplitude modulation scheme is based upon the principle of recognizing that a vestigial sideband signal may be regarded and treated as an offset-keyed QAM signal. The detector comprises a tuner for tuning to a center frequency symmetrically displaced within the transmitted digital data signal frequency spectrum and a decoder circuit selectively operating to reconstruct the transmitted digital data stream according to the duration of a transmitted data symbol. A related method of demodulating and decoding a modulated digital data stream comprises analogous steps of tuning to a center carrier frequency and selectively switching between in phase and quadrature arms of the demodulator such that the switch resides in one position or the other for a duration equal to half the duration of a transmitted data symbol. A related modulator for modulating a digital data signal either according to a vestigial sideband or quadrature amplitude modulation scheme comprises a switch for selectively switching an input digital data signal between real and imaginary arms and a modulator for modulating at center frequency. In one modulator embodiment, a noise cancellation circuit may be coupled between the real and imaginary arms.

摘要翻译： 用于解调和解码根据残留边带或正交幅度调制方案调制的数字数据信号的同步检测器基于识别残留边带信号可被视为偏移键控QAM信号的原理。 检测器包括用于调谐到发送的数字数据信号频谱内对称位移的中心频率的调谐器，以及选择性地操作以根据所发送的数据符号的持续时间重建所发送的数字数据流的解码器电路。 解调和解码调制数字数据流的相关方法包括调谐到中心载波频率和选择性地在解调器的同相和正交臂之间切换的类似步骤，使得开关驻留在一个位置或另一个位置，持续时间等于 传输数据符号的持续时间的一半。 用于根据残留边带或正交幅度调制方案调制数字数据信号的相关调制器包括用于选择性地切换实际臂和虚臂之间​​的输入数字数据信号的开关和用于在中心频率调制的调制器。 在一个调制器实施例中，噪声消除电路可以耦合在实际臂和假想臂之间。

公开(公告)号：US5271041A

公开(公告)日：1993-12-14

申请号：US852277

申请日：1992-03-16

申请人： Leo Montreuil

发明人： Leo Montreuil

IPC分类号： H04L25/497 ,  H04L27/06

CPC分类号： H04L25/497

摘要： A digital audio communication system includes a digital modulation and demodulation scheme which efficiently uses the bandwidth and channel spacing of a cable television system. A 30 channel digital bit stream is demultiplexed into six groups of five channels. Each group of channels thereafter modulates a carrier by a quadrature partial response (QPR) process. The QPR signal, an amplitude modulated, double sideband, carrier suppressed (AM DSBSC) signal, is then transmitted over the cable system to a multiplicity of subscribers, each of which has a QPR demodulator. The demodulators are of the decision feedback type having a modified Costas loop carrier recovery circuit. The grouping of an odd number (five) of digital audio channels per QPR modulator minimizes error propagation due to the correlative QPR demodulation process. The decision feedback decoding is implemented in simple current nodes where a bilevel output from the decoded data is subtracted from a tertiary level output of a mixer. The resulting bilevel current is converted to a voltage, filtered, and limited to produce a logic output level. The modified Costas loop provides an error voltage based upon the difference of the received data states versus the nominal data states and the quadrant the data occupies. The error voltage is generated by differencing the outputs of two analog switches which have as their inputs analog signals representative of the amplitude level of the data and its inverse of one phase. The sign of the data bit of the opposite phase is used to control the switch and thus select which signal is used.

摘要翻译： 数字音频通信系统包括有效地使用有线电视系统的带宽和信道间隔的数字调制和解调方案。 30通道数字比特流被解复用为六组五个通道。 此后，每组信道通过正交部分响应（QPR）处理来调制载波。 然后，通过电缆系统将QPR信号（幅度调制的，双边带，载波抑制（AM DSBSC））传输到多个用户，每个用户具有QPR解调器。 解调器具有具有经修改的科斯塔斯环路载波恢复电路的判决反馈类型。 每个QPR调制解调器的奇数（5）个数字音频信道的分组使由于相关QPR解调过程引起的误差传播最小化。 决策反馈解码在简单的电流节点中实现，其中来自解码数据的双向输出从混频器的第三级输出中减去。 所得到的双电平电流被转换成电压，被滤波并被限制以产生逻辑输出电平。 经修改的科斯塔斯循环基于接收的数据状态与标称数据状态和数据占用的象限的差异提供误差电压。 误差电压通过差分两个模拟开关的输出产生，这两个模拟开关的输入具有代表数据幅度电平的模拟信号及其一相的反相。 反相的数据位的符号用于控制开关，从而选择使用哪个信号。