摘要:
A non-coherent demodulator 1 multiplies a modulated intermediate frequency (IF) signal with a signal from a local oscillator 2 to produce a first pseudo baseband signal having frequency error. The first pseudo baseband signal is supplied to a wide band PLL type demodulator 15. A low-pass filter 26 removes noise component from a first control signal from a loop filter 19 in the wide band PLL type demodulator 15 to produce a second control signal. Multipliers 24 and 25 multiply the first pseudo baseband signal with an output of a voltage-controlled oscillator 27 controlled by the second control signal to produce a second pseudo baseband signal having smaller frequency error. The second pseudo baseband signal is supplied to a narrow band demodulator 14 and converted into a baseband signal.
摘要:
A phase locked loop circuit for use in a heterodyne receiver for stably demodulating a carrier-suppressed double-sideband signal such as a 2-phase or 4-phase PSK signal. The phase locked loop circuit comprises a reference oscillator oscillating at a frequency corresponding to an intermediate frequency, and the frequency difference between the reference frequency and the input frequency is detected by a Costas loop, a signal indicative of the frequency difference being fed back to a local oscillator through a loop filter thereby stabilizing the intermediate frequency.
摘要:
A direct conversion Binary FSK radio receiver has an AFC loop comprising an Exclusive-Or phase detector 104 responsive to the I.sub.3 and Q.sub.3 signals. I and Q filters 100, 101 are not identical but have different frequency-phase characteristics such that their phase shifts are identical when the local oscillator 102 is correctly tuned and differ when the local oscillator is off-tune. Detector 104 detects the change of phase and applies a control signal to local oscillator 102 such as to return the local oscillator frequency to the correct value. Alternatively, identical filters may be used in the I and Q channels, circuits having different phase shifts being coupled between the I.sub.3 and Q.sub.3 signals and the inputs of the phase detector 104.
摘要:
An FM receiver for the reception of digital data modulated on a Subsidiary Communication Authorization (SCA) subcarrier is provided with automatic tuning capability and a coherent demodulator for minimizing noise, distortion and interference. The FM receiver is tuned automatically to minimize the measured amplitude of noise and distortion at the high frequency end of the spectrum of the FM demodulator output, above the frequencies of the SCA signal. The SCA signal is tuned by a heterodyne circuit including a balanced modulator, a voltage-controlled oscillator (VCO), and a bandpass filter. The VCO is automatically tuned to maximize the measured amplitude of the SCA signal selected by the bandpass filter. For coherent detection of BPSK (Binary-Phase-Shift-Keying), the coherent demodulator is preferably and kind of data-aided Costas loop in which digital logic circuits perform phase shifting, phase detecting, a multiplying functions. The feedback of the phase error signal is preferably inhibited whenever the signal-to-noise ratio falls below the level which ensures phase-lock, for example, by inhibiting feedback whenever the amplitude of the filtered in-phase signal in the Costas loop fails to exceed a predetermined threshold level. Preferably the phase error signal is fed back through an integrating low-pass filter to control the VCO of the heterodyne circuit, and is fed back through a bandpass filter to control the oscillator of the Costas loop.
摘要:
A frequency discriminator having a wide capture band is shown to comprise, in addition to a conventional phase detector having two channels fed by a signal whose frequency is to be determined (the first one of the channels containing a tuned circuit operative to shift the phase of the signal in accordance with the difference between the frequency of the signal and the center frequency of the tuned circuit and the second one of the channels containing a phase shifter operative to shift the phase of the signal by 90.degree. regardless of the frequency of the signal), a compensating circuit operative substantially to equalize the amplitudes of the signals applied to the phase detector, the compensating circuit including an amplifier in the first one of the channels to amplify the signal out of the tuned circuit, the gain of the amplifier being controlled by a signal indicative of the difference between the amplitudes of the signals fed to the phase detector.
摘要:
A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.
摘要:
A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.
摘要:
A frequency-agile synchronous demodulator for demodulating a carrier signal. The carrier signal is decomposed into in-phase and quadrature-phase components. Using the in-phase and quadrature-phase components, a first error signal is produced representing the phase difference between the carrier signal and a local oscillator signal. A reference signal, related to the frequency of the carrier signal by a factor N, is also input to the frequency-agile synchronous demodulator. The local oscillator signal is scaled by the factor N, and compared to the reference frequency signal in a phase detector. The phase detector produces a second error signal representing the phase difference between the reference signal and the local oscillator signal. The first error signal is integrated and summed with the second error signal. The resultant sum signal is integrated and input to the local oscillator for controlling the frequency and phase thereof. Generation of the second error signal ensures that the frequency-agile synchronous demodulator locks to the correct carrier frequency signal, rather than another signal on an adjacent frequency. The first error signal ensures a phase-locked condition.