公开(公告)号：US07920652B2

公开(公告)日：2011-04-05

申请号：US11005073

申请日：2004-12-07

申请人： Shigenori Hayase ,  Kazuyuki Hori

发明人： Shigenori Hayase ,  Kazuyuki Hori

IPC分类号： H04L27/00

CPC分类号： H03D7/163 ,  H03D3/245 ,  H04L27/3863

摘要： To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.

摘要翻译： 检测正交解调器的同相和正交信号之间的相位失配。 可以使用通过低通滤波器去除乘法器的输出的高频分量而获得的信号来检测相位失配，该输出是通过第一高通滤波器去除低频分量的同相信号的乘积 通过第二高通滤波器去除低频分量的正交信号。

公开(公告)号：US07079598B2

公开(公告)日：2006-07-18

申请号：US10891586

申请日：2004-07-15

申请人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

发明人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

IPC分类号： H04B17/00

CPC分类号： H04L27/3836 ,  H03D3/245

摘要： A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

摘要翻译： 数字解调器，其使用复值锁相环（CPPL）相干地解调低中频或零中频复信号。 CPPL包括数控振荡器，四个乘法器和两个组合器，以提供独立的相位/频率和幅度输出。 CPLL在没有环路滤波器的一阶PLL动态中展现了到NCO的反馈环路。 然而，具有一个或多个极点的滤波器可以包括在反馈电路中以呈现第二和第二或更高阶PLL动态。 CPLL允许相干解调极低的FM调制指数，从而输入频率漂移可能大于频率偏差。 它也可以用于相干解调具有组合幅度和相位特性的信号。

公开(公告)号：US5640126A

公开(公告)日：1997-06-17

申请号：US585242

申请日：1996-01-11

申请人： Pascal Mellot

发明人： Pascal Mellot

IPC分类号： H04N5/60 ,  H03D3/02 ,  H03D3/24 ,  H03L7/087 ,  H03L7/099 ,  H03L7/107 ,  H03L7/113 ,  H04B1/26 ,  H03D3/00 ,  H03L7/093

CPC分类号： H03L7/107 ,  H03D3/241 ,  H03D3/245 ,  H03L7/099 ,  H03L7/113 ,  H03D2200/0027 ,  H03L2207/06 ,  H03L7/087

摘要： The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

摘要翻译： 本发明提供一种解调PLL，其中：由控制电路控制的开关的第一位置分别在混频器和LP滤波器的输出端连接到振荡器的高增益和低增益输入端，当输入端的频率信号 的混频器没有充分收敛，即在PLL调谐模式期间; 当混频器输入端的频率信号和滤波器的输入和输出信号电平时，开关的第二位置分别将混频器和LP滤波器的输出端连接到振荡器的低增益和高增益输入 已经充分收敛，即在PLL解调模式期间。

公开(公告)号：US4642573A

公开(公告)日：1987-02-10

申请号：US783521

申请日：1985-10-03

申请人： Tsutomu Noda ,  Keiro Shinkawa ,  Nobutaka Amada

发明人： Tsutomu Noda ,  Keiro Shinkawa ,  Nobutaka Amada

IPC分类号： H03D1/24 ,  H03D3/24 ,  H03D7/16 ,  H03L7/087 ,  H04L27/227 ,  H03D3/02 ,  H04L27/22

CPC分类号： H04L27/2272 ,  H03D3/242 ,  H03D3/245 ,  H03L7/087 ,  H03D2200/0031 ,  H03D7/161

摘要： A phase locked loop circuit for use in a heterodyne receiver for stably demodulating a carrier-suppressed double-sideband signal such as a 2-phase or 4-phase PSK signal. The phase locked loop circuit comprises a reference oscillator oscillating at a frequency corresponding to an intermediate frequency, and the frequency difference between the reference frequency and the input frequency is detected by a Costas loop, a signal indicative of the frequency difference being fed back to a local oscillator through a loop filter thereby stabilizing the intermediate frequency.

摘要翻译： 一种用于外差接收机的锁相环电路，用于稳定解调诸如2相或4相PSK信号的载波抑制双边带信号。 锁相环电路包括以对应于中频的频率振荡的参考振荡器，并且通过科斯塔斯回路检测参考频率与输入频率之间的频率差，表示频差的信号被反馈到 本地振荡器通过环路滤波器，从而稳定中频。

公开(公告)号：US4185243A

公开(公告)日：1980-01-22

申请号：US885841

申请日：1978-03-13

申请人： Kenneth H. Brown

发明人： Kenneth H. Brown

IPC分类号： H03D3/24 ,  H03G3/34 ,  H04B1/16

CPC分类号： H03D3/245 ,  H03G3/34 ,  H03D2200/0025

摘要： The disclosed signal generating apparatus and method is suitable for use in combination with a PM receiver to provide a standby signal for a signal processor. The standby signal system includes a clipper connected to the receiver IF; a coherent amplitude detector coupled between the clipper and a gain controlled amplifier; and a trigger circuit coupled between the coherent amplitude detector and the signal processor. The trigger circuit provides a standby signal in response to the level of the output signal of the coherent amplitude detector passing through a predetermined threshold level in response to the clipper limiting on a selected signal-to-noise ratio which occurs before the information signal becomes undesirably weak.

摘要翻译： 所公开的信号发生装置和方法适合与PM接收机组合使用，以为信号处理器提供备用信号。 备用信号系统包括连接到接收机IF的限幅器; 耦合在限幅器和增益控制放大器之间的相干幅度检测器; 以及耦合在相干幅度检测器和信号处理器之间的触发电路。 触发电路响应于相关幅度检测器的输出信号的电平响应于对信息信号变得不期望地发生的所选择的信噪比进行限幅而响应于预定阈值电平而提供备用信号 弱。

公开(公告)号：US20060056546A1

公开(公告)日：2006-03-16

申请号：US11005073

申请日：2004-12-07

申请人： Shigenori Hayase ,  Kazuyuki Hori

发明人： Shigenori Hayase ,  Kazuyuki Hori

IPC分类号： H04L27/22 ,  H03D3/00 ,  H04J11/00

CPC分类号： H03D7/163 ,  H03D3/245 ,  H04L27/3863

摘要： To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.

摘要翻译： 检测正交解调器的同相和正交信号之间的相位失配。 可以使用通过低通滤波器去除乘法器的输出的高频分量而获得的信号来检测相位失配，该输出是通过第一高通滤波器去除低频分量的同相信号的乘积 通过第二高通滤波器去除低频分量的正交信号。

公开(公告)号：US06275542B1

公开(公告)日：2001-08-14

申请号：US09070154

申请日：1998-04-30

申请人： Hiroshi Katayama ,  Katsuaki Abe ,  Yasumi Imagawa

发明人： Hiroshi Katayama ,  Katsuaki Abe ,  Yasumi Imagawa

IPC分类号： H03D300

CPC分类号： H03D3/245 ,  H03D3/007

摘要： A direct conversion receiver includes a local oscillator for generating a first local oscillator signal having a variable frequency. A 90° phase shifter operates for shifting a phase of the first local oscillator signal by 90° to convert the first local oscillator signal into a second local oscillator signal. A first mixer operates for mixing a received RF signal and the first local oscillator signal. A second mixer operates for mixing the received RF signal and the second local oscillator signal. A first low pass filter processes an output signal of the first mixer. The first low pass filter has a controllable cutoff frequency. A second low pass filter processes an output signal of the second mixer. The second low pass filter has a controllable cutoff frequency. A demodulator recovers an information signal represented by the received RF signal from output signals of the first and second low pass filters. A frequency error detector operates for detecting an error between a frequency of a carrier of the received RF signal and the frequency of the first local oscillator signal in response to the information signal recovered by the demodulator. An oscillator controller operates for controlling the frequency of the first local oscillator signal in response to the error detected by the frequency error detector. A filter controller operates for controlling the cutoff frequencies of the first and second low pass filters in response to the error detected by the frequency error detector.

摘要翻译： 直接转换接收机包括用于产生具有可变频率的第一本机振荡器信号的本地振荡器。 90°移相器用于将第一本地振荡器信号的相位移位90°以将第一本机振荡器信号转换为第二本机振荡器信号。 第一混频器用于混合接收的RF信号和第一本地振荡器信号。 第二混频器用于混合接收到的RF信号和第二本地振荡器信号。 第一低通滤波器处理第一混频器的输出信号。 第一个低通滤波器具有可控的截止频率。 第二低通滤波器处理第二混频器的输出信号。 第二低通滤波器具有可控的截止频率。 解调器从第一和第二低通滤波器的输出信号中恢复由接收的RF信号表示的信息信号。 频率误差检测器用于响应于由解调器恢复的信息信号来检测接收的RF信号的载波的频率与第一本地振荡器信号的频率之间的误差。 振荡器控制器用于响应于由频率误差检测器检测到的误差来控制第一本地振荡器信号的频率。 滤波器控制器用于响应于由频率误差检测器检测到的误差来控制第一和第二低通滤波器的截止频率。

公开(公告)号：US5596606A

公开(公告)日：1997-01-21

申请号：US223223

申请日：1994-04-05

申请人： Leo Montreuil

发明人： Leo Montreuil

IPC分类号： H04N5/455 ,  H03C3/04 ,  H03C3/40 ,  H03D1/22 ,  H03D1/24 ,  H03D3/00 ,  H03D3/24 ,  H04L27/00 ,  H04L27/02 ,  H04L27/06 ,  H04L27/38 ,  H04N5/44

CPC分类号： H04L27/38 ,  H03C3/40 ,  H03D1/2254 ,  H04L27/0008 ,  H04L27/02 ,  H04L27/3836 ,  H04N5/4401 ,  H03C3/04 ,  H03D1/2245 ,  H03D2200/0031 ,  H03D3/007 ,  H03D3/245

摘要： A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.

摘要翻译： 同步检测器具有第一和第二混频器电路和压控振荡器。 压控振荡器将本地振荡器信号直接提供给第二混频器电路，并且通过相变器间接地提供给第一混频器电路。 第一和第二混频器电路的输出在组合器电路中组合以产生抖动消除的输出信号。 抖动消除输出信号在环路滤波器中滤波，并施加到压控振荡器以控制本地振荡器信号的频率和相位。 组合器电路包括加法器和抖动消除滤波器。 抖动消除滤波器优选地是与所检测的信号的频谱匹配的高通滤波器。 第一混频器电路的输出通过高通滤波器进入夏季的一个输入端，而第二混频器电路的输出被传递到夏季的第二输入端。 夏季的输出将传递给环路滤波器。

公开(公告)号：US5592513A

公开(公告)日：1997-01-07

申请号：US473949

申请日：1995-06-07

申请人： Leo Montreuil

发明人： Leo Montreuil

IPC分类号： H04N5/455 ,  H03C3/04 ,  H03C3/40 ,  H03D1/22 ,  H03D1/24 ,  H03D3/00 ,  H03D3/24 ,  H04L27/00 ,  H04L27/02 ,  H04L27/06 ,  H04L27/38 ,  H04N5/44 ,  H03C1/04 ,  H04L27/36

CPC分类号： H04L27/38 ,  H03C3/40 ,  H03D1/2254 ,  H04L27/0008 ,  H04L27/02 ,  H04L27/3836 ,  H04N5/4401 ,  H03C3/04 ,  H03D1/2245 ,  H03D2200/0031 ,  H03D3/007 ,  H03D3/245

摘要： A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.

摘要翻译： 同步检测器具有第一和第二混频器电路和压控振荡器。 压控振荡器将本地振荡器信号直接提供给第二混频器电路，并且通过相变器间接地提供给第一混频器电路。 第一和第二混频器电路的输出在组合器电路中组合以产生抖动消除的输出信号。 抖动消除输出信号在环路滤波器中滤波，并施加到压控振荡器以控制本地振荡器信号的频率和相位。 组合器电路包括加法器和抖动消除滤波器。 抖动消除滤波器优选地是与所检测的信号的频谱匹配的高通滤波器。 第一混频器电路的输出通过高通滤波器进入夏季的一个输入端，而第二混频器电路的输出被传递到夏季的第二输入端。 夏季的输出将传递给环路滤波器。

公开(公告)号：US4881042A

公开(公告)日：1989-11-14

申请号：US147433

申请日：1988-01-25

申请人： Sung-Ki Min ,  Chan-Kyu Myung ,  Ki-Ho Shin

发明人： Sung-Ki Min ,  Chan-Kyu Myung ,  Ki-Ho Shin

IPC分类号： H03D3/02 ,  H03B5/12 ,  H03D3/24 ,  H03D7/00 ,  H03L7/06 ,  H03L7/10

CPC分类号： H03D3/245 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1243

摘要： A FM detection system using a phase locked loop (PPL 20) and including: a wave shaping comparator (7) for accepting a signal V.sub.CO2 from a voltage controlled oscillator (4) which is 90.degree. out of phase with a control signal V.sub.CO1 from the voltage controlled oscillator (4), the comparator reshaping the signal to a square wave; an in-lock detector (8) for accepting the square wave and a frequency modulated input signal (VFM) to provide a sum frequency and a difference frequency; a low-pass filter (9) cutting off the sum frequency component, and filtering out the difference frequency signal when the PLL (20) is unlocked; a comparator (10) for comparing the output of the low-pass filter (9) with a reference voltage (V.sub.REF1), and providing a constant logic level when the PLL (20) is locked, or providing a clock pulse corresponding to the difference frequency when the PLL (20) is unlocked; a ripple counter (11) for counting the clock pulse and providing a binary signal output reflective of the count; a D/A converter (12) for accepting the binary output to provide an analogue current; and the oscillation frequency of the voltage controlled oscillator (4) being controlled in response to the output voltage from an amplifier (3) of PLL (20) and the output current of the D/A converter (12). A large detection output is attained in spite of a small loop gain.

摘要翻译： 一种使用锁相环（PPL 20）的FM检测系统，包括：波形整形比较器（7），用于从与来自该控制信号VCO1的控制信号VCO1相差90度的压控振荡器（4）接收信号VCO2 压控振荡器（4），比较器将信号重新整形为方波; 用于接受方波的锁定检测器（8）和调频输入信号（VFM）以提供和频和差频; 切断所述和频分量的低通滤波器（9），并且在所述PLL（20）解锁时滤除所述差频信号; 比较器（10），用于将低通滤波器（9）的输出与参考电压（VREF1）进行比较，并且当PLL（20）被锁定时提供恒定的逻辑电平，或者提供与差分对应的时钟脉冲 PLL（20）解锁时的频率; 波纹计数器（11），用于对时钟脉冲进行计数并提供反映计数的二进制信号输出; D / A转换器（12），用于接受二进制输出以提供模拟电流; 并且受压控振荡器（4）的振荡频率响应于来自PLL（20）的放大器（3）的输出电压和D / A转换器（12）的输出电流而被控制。 尽管环路增益较小，但仍能获得较大的检测输出。