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1.发明授权Pixel data path for high performance raster displays with all-point-addressable frame buffers 失效具有全点可寻址帧缓冲区的高性能光栅显示的像素数据路径
公开(公告)号：US4823286A
公开(公告)日：1989-04-18
申请号：US13847
申请日：1987-02-12
CPC分类号： G09G5/393
摘要： A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality "antialiased" text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the "burst" mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.
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公开(公告)号：US4870406A
公开(公告)日：1989-09-26
申请号：US13842
申请日：1987-02-12
申请人： Satish Gupta , Leon Lumelsky , Robert L. Mansfield , Hector G. Romero, Jr. , Marc Segre , Alexander K. Spencer , Joe C. St. Clair , James D. Wagoner
发明人： Satish Gupta , Leon Lumelsky , Robert L. Mansfield , Hector G. Romero, Jr. , Marc Segre , Alexander K. Spencer , Joe C. St. Clair , James D. Wagoner
CPC分类号： G09G5/393
摘要： A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.
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公开(公告)号：US4808986A
公开(公告)日：1989-02-28
申请号：US13840
申请日：1987-02-12
CPC分类号： G09G5/393
摘要： A graphics display system including a circuit that receives graphics information to be displayed and a memory that stores the graphics information in a memory array that includes a portion that directly corresponds to the image area for display. The memory provides a single access operation to the array during a single memory cycle. Circuitry is provided that is connected to the receiving means and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle (wherein N and M are integers each greater than one). A display is connected to the memory that displays the graphics information contained in the image area array portion of the memory. The graphics display system further includes the capability to provide a patterned line intersection where the continuity of the line pattern is maintained along the intersection of the lines.
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公开(公告)号：US4837563A
公开(公告)日：1989-06-06
申请号：US013841
申请日：1987-02-12
摘要： In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter is performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a first predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reacing to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms. This counter circuit capability increases the speed at which line draw functions and bit block transfer functions can be accomplished in a graphics display system processor.
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5.发明授权
公开(公告)号：US4916301A
公开(公告)日：1990-04-10
申请号：US298792
申请日：1989-01-17
IPC分类号： G09G5/393
CPC分类号： G09G5/393
摘要： A processing system is provided that includes an external device connected to a processor. The external device has the capability of responding to external device commands wherein each of these external device commands is performed within at least one fixed time cycle. The processor provides these external device commands and, further, includes the means for executing instructions that not only specify the external device commands but also specify at least one internal command to be performed by the processor simultaneously with the performance of the external device command and within the same fixed time cycle. In the disclosed embodiment, a graphics display system is provided that includes a system processor, a graphic processor, a graphics memory and a display device. The graphics processor receives instructions from the system processor which specifies commands to be executed by both the graphics processor and the graphics memory. Each graphics memory command is executed within a fixed time cycle simultaneously with the execution of a corresponding graphics processor command executed within the graphics processor.
摘要翻译： 提供了一种包括连接到处理器的外部设备的处理系统。 外部设备具有响应外部设备命令的能力，其中这些外部设备命令中的每一个在至少一个固定时间周期内执行。 处理器提供这些外部设备命令，并且还包括用于执行不仅指定外部设备命令的指令的装置，而且还指定要由处理器执行的至少一个内部命令，同时执行外部设备命令， 相同的固定时间周期。 在所公开的实施例中，提供了包括系统处理器，图形处理器，图形存储器和显示装置的图形显示系统。 图形处理器从系统处理器接收指令，该指令指定要由图形处理器和图形存储器执行的命令。 每个图形存储器命令在固定时间周期内与执行在图形处理器内执行的相应图形处理器命令同时执行。
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公开(公告)号：US5182554A
公开(公告)日：1993-01-26
申请号：US629864
申请日：1990-12-18
申请人： John M. Kaiser , Joe C. St. Clair
发明人： John M. Kaiser , Joe C. St. Clair
IPC分类号： G06F15/163 , G06F13/14 , G06F13/38 , H04Q3/52
CPC分类号： H04Q3/52
摘要： A communication system for providing a communication path between two of a plurality of devices. A first port is provided that is connected to at least one device. A second port is provided connected to a second device. A switch is provided connecting the two ports for communications connection between the ports in response to commands form the devices to each other. The switch includes the capability to monitor communications between the devices and to determine when a change is to be made in the communications path and then to make the change accordingly.
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公开(公告)号：US5301278A
公开(公告)日：1994-04-05
申请号：US873880
申请日：1992-04-23
IPC分类号： G06F13/16 , G11C7/22 , G11C8/18 , G11C11/4076 , G06F13/10
CPC分类号： G11C7/22 , G06F13/1689 , G06F13/1694 , G11C11/4076 , G11C8/18
摘要： A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.
摘要翻译： 灵活的动态存储器控制器，其可操作与动态RAMS具有广泛的操作特性。 这些特征包括各种存储器功能的不同操作速度和存储器的使用。 在状态机中，使用专用寄存器来控制操作顺序以及必须插入多长时间的延迟。 根据在给定时间访问的存储器的类型和请求的来源，存储器控制器动态地确定延迟。
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8.发明授权Apparatus and method for relating a point of selection to an object in a graphics display system 失效将选择点与图形显示系统中的对象相关联的装置和方法
公开(公告)号：US5329613A
公开(公告)日：1994-07-12
申请号：US58991
申请日：1993-05-06
CPC分类号： G06F3/04842 , G06T15/30
摘要： Apparatus and methods for picking three dimensional objects from images depicted on a video display. The displayed objects are selectively rerendered. During such rerendering the object pixels are compared in depth to the data in a Z buffer for determining visibility. The number and size of the objects subject to rerendering by the rasterization processor is constrained by using the front end graphics processor to define object extents and by rerendering only extents which have been clipped to the boundaries of the pick window. The rerendering operation does not alter the three dimensional graphics image stored in and repetitively scanned from the frame buffer. Selection between multiple objects within the pick window can include a weighted comparison using a pick plane memory to store visibility data by object.
摘要翻译： 用于从视频显示器上描绘的图像中拾取三维物体的装置和方法。 显示的对象被选择性地重新呈现。 在这种重新渲染期间，将目标像素与Z缓冲器中的数据进行深度比较以确定可视性。 通过使用前端图形处理器来定义对象范围并且仅重新渲染已经被剪辑到选择窗口的边界的范围，限制由光栅化处理器重新渲染的对象的数量和大小。 退回操作不会改变存储在帧缓冲器中并重复扫描的三维图形图像。 选择窗口内的多个对象之间的选择可以包括使用拾取平面存储器按对象存储可见性数据的加权比较。
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公开(公告)号：US5113180A
公开(公告)日：1992-05-12
申请号：US183795
申请日：1988-04-20
CPC分类号： G09G5/36 , G06F12/1081 , G09G5/14 , G06F12/08 , G09G5/39
摘要： A display control such as a virtual display adapter allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory. This large area of memory includes system memory, and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.
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公开(公告)号：US5319395A
公开(公告)日：1994-06-07
申请号：US54701
申请日：1993-04-28
摘要： A pixel-depth converter for source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth. A packed-pixel-data depacker circuit receives source-pixel data words having a packed-pixel data format from a source-pixel-data memory and transmits the data words depacked-pixel-data-word-component-by-depacked-pixel-data-word-component in accordance with a user selected pixel-depth-conversion scale factor. A pixel-data-conversion-table storage circuit stores selectable depth-altering pixel-data-conversion data in locations having conversion-table read addresses which are associated with values corresponding to the selected pixel-depth-conversion scale factor. The storage circuit includes independently-operable converted-data-read parallel output ports and associated conversion-table read-address input ports. Conversion-lookup addresses may be applied independently in parallel to the plurality of conversion-table storage circuit. Stored conversion data can be read in parallel from the associated converted-data-read output ports. Input ports of multiplexers are connected to corresponding terminal subsets of the depacker circuit which are associated with different pixel-depth-conversion scale factor. A conversion-lookup address output port of each multiplexer is connected to an associated read-address input port of the storage circuit. The multiplexer control-signal input ports are connectable to a bus for receiving a scale-factor-selection signal which specifies the desired pixel-depth-conversion scale factor and corresponding depacked-source-pixel-data portions.
摘要翻译： 用于源像素数据的像素深度转换器，其具有源目标像素深度与目标像素数据的距离不同于源像素深度的目标像素深度。 压缩像素数据去除器电路从源像素数据存储器接收具有压缩像素数据格式的源像素数据字，并且将数据字解码像素数据字分量逐个像素数据存储器， 数据字分量根据用户选择的像素深度转换比例因子。 像素数据转换表存储电路将可选择的深度改变像素数据转换数据存储在具有与所选择的像素深度转换比例因子对应的值相关联的转换表读取地址的位置中。 存储电路包括可独立操作的转换数据读取并行输出端口和相关联的转换表读地址输入端口。 转换查找地址可以独立地并行地应用于多个转换表存储电路。 存储的转换数据可以从相关联的转换数据读取输出端口并行读取。 多路复用器的输入端口连接到与不同像素深度转换比例因子相关联的存储器电路的相应终端子集。 每个多路复用器的转换查找地址输出端口连接到存储电路的相关读取地址输入端口。 多路复用器控制信号输入端口可连接到总线，用于接收指定期望的像素深度转换比例因子和相应的解码源像素数据部分的比例因子选择信号。
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