公开(公告)号：US08112249B2

公开(公告)日：2012-02-07

申请号：US12341431

申请日：2008-12-22

申请人： Leonid Gurov ,  Alexander Chufarovsky ,  Gil Balog

发明人： Leonid Gurov ,  Alexander Chufarovsky ,  Gil Balog

IPC分类号： G06F17/18

CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification defining a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method including: computing an estimated maximum test range, at a given confidence level, on a validation set including a subset of the population of semiconductor devices, the estimated maximum test range including the range of values into which all results from performing the test on the set will statistically fall at the given confidence level and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range.

摘要翻译： 用于减少时间的参数测试时间缩短方法用于在半导体器件群体上进行测试程序流程，该测试程序流程包括具有定义已知通过值范围的规范的至少一个参数测试，其特征在于测试结果 如果结果在已知通过值范围内，则被认为是传递结果，该方法包括：以给定的置信水平计算包括半导体器件群体的子集的验证集合的估计最大测试范围，估计的最大值 测试范围包括值的范围，在该范围内，对集合进行测试的所有结果将统计地落在给定的置信水平，并且至少部分地至少部分地基于估计的最大测试范围的比较来禁用至少一个参数测试 和已知通过值范围。

公开(公告)号：US08781773B2

公开(公告)日：2014-07-15

申请号：US13164910

申请日：2011-06-21

申请人： Leonid Gurov ,  Alexander Chufarovsky ,  Gil Balog ,  Reed Linde

发明人： Leonid Gurov ,  Alexander Chufarovsky ,  Gil Balog ,  Reed Linde

IPC分类号： G01N37/00 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods, systems, computer-program products and program-storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test-range. One method comprises: attaining results generated from a parametric test on semiconductor devices included in a control set; selecting from the semiconductor devices at least one extreme subset including at least one of a high-scoring subset and a low-scoring subset; plotting at least results of the at least one extreme subset; fitting a plurality of curves to a plurality of subsets of the results; extending the curves to the zero-probability axis for the low-scoring subset or the one-probability axis for the high-scoring subset to define a corresponding plurality of intersection points; defining an estimated maximum test range based on at least one of the intersection points; and determining whether or not to perform an action based at least partly on the estimated maximum test range.

摘要翻译： 用于确定是否至少部分地基于估计的最大测试范围来执行动作的方法，系统，计算机程序产品和程序存储设备。 一种方法包括：获得由包括在控制集中的半导体器件的参数测试产生的结果; 从所述半导体器件中选择至少一个极端子集，其包括高得分子集和低得分子集中的至少一个; 绘制至少一个极端子集的至少结果; 将多个曲线拟合到所述结果的多个子集中; 将所述曲线延伸到所述低得分子集的零概率轴或所述高分数子集的单概率轴，以定义相应的多个交点; 基于所述交点中的至少一个来定义估计的最大测试范围; 以及至少部分地基于所估计的最大测试范围来确定是否执行动作。

公开(公告)号：US20100161276A1

公开(公告)日：2010-06-24

申请号：US12341431

申请日：2008-12-22

申请人： Leonid Gurov ,  Alexander Chufarovsky ,  Gil Balog

发明人： Leonid Gurov ,  Alexander Chufarovsky ,  Gil Balog

IPC分类号： G06F17/18

CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification which defines a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method comprising, for at least one parametric test, computing an estimated maximum test range, at a given confidence level, on a validation set comprising a subset of the population of semiconductor devices, the estimated maximum test range comprising the range of values into which all results from performing the test on the set will statistically fall at the given confidence level, the validation set defining a complementary set including all semiconductors included in the population and not included in the validation set; and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range.

摘要翻译： 一种用于减少时间的参数测试时间缩短方法用于对一组半导体器件进行测试程序流程，所述测试程序流程包括至少一个具有定义已知通过值范围的规范的参数测试，其特征在于， 如果结果落在已知的通过值范围内，则测试被认为是传递结果，该方法包括对于至少一个参数测试，在给定的置信水平下，计算估计的最大测试范围在包括 估计的最大测试范围包括其中对集合进行测试的所有结果将统计学下降到给定的置信水平的值的范围，所述验证集定义包括所述群体中包括的所有半导体的互补集合，以及 不包括在验证集中; 并且至少部分地至少部分地基于估计的最大测试范围和已知通过值范围的比较来禁用所述至少一个参数测试。

公开(公告)号：US20080114558A1

公开(公告)日：2008-05-15

申请号：US12007747

申请日：2008-01-15

申请人： Nir Erez ,  Gil Balog

发明人： Nir Erez ,  Gil Balog

IPC分类号： G06F19/00

CPC分类号： G01R31/2894 ,  G01R31/287 ,  G11C29/56 ,  G11C29/56008

摘要： A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and other population(s). The method includes the step of associating test flows to the populations. Each test flow includes stress testing sequence. The stress testing sequence for the quality or reliability fail candidate population includes a stress test of increased duration compared to duration of a stress test in the test flow of the other population. The stress test sequence for the other population includes a stress test of increased voltage compared to corresponding operating voltage specification for a semiconductor unit. The method further includes the step of applying, within a sort testing stage, the corresponding test flow to the populations and identifying any unit which failed the stress sequence.

公开(公告)号：US20070233629A1

公开(公告)日：2007-10-04

申请号：US11396938

申请日：2006-04-04

申请人： Gil Balog

发明人： Gil Balog

IPC分类号： G06N5/02

CPC分类号： G01R31/31912 ,  G01R31/318314 ,  G06N5/025

摘要： Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.

摘要翻译： 半导体测试方法和系统。 在一个实施例中，半导体测试方法包括以下阶段中的一个或多个：定义与半导体测试有关的规则，验证规则，将规则与其他规则绑定，将规则与其他规则相关联，发布规则，实现规则 ，并对有关规则采取后续行动。 在一个实施例中，半导体测试系统包括以下模块中的一个或多个：规则创建模块，分析模块，模拟模块，实时生产模块和离线生产模块 ）。 在一个实施例中，用户友好的图形用户界面可用于定义规则的构建块和/或用于查看规则所属的类别的可选层次结构。

公开(公告)号：US08069130B2

公开(公告)日：2011-11-29

申请号：US12493460

申请日：2009-06-29

申请人： Gil Balog

发明人： Gil Balog

IPC分类号： G06F17/00 ,  G06N5/02

CPC分类号： G01R31/31912 ,  G01R31/318314 ,  G06N5/025

摘要： Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.

摘要翻译： 半导体测试方法和系统。 在一个实施例中，半导体测试方法包括以下阶段中的一个或多个：定义与半导体测试有关的规则，验证规则，将规则与其他规则绑定，将规则与其他规则相关联，发布规则，实现规则 ，并对有关规则采取后续行动。 在一个实施例中，半导体测试系统包括以下模块中的一个或多个：规则创建模块，分析模块，模拟模块，实时生产模块和离线生产模块 ）。 在一个实施例中，用户友好的图形用户界面可用于定义规则的构建块和/或用于查看规则所属的类别的可选层次结构。

公开(公告)号：US07737716B2

公开(公告)日：2010-06-15

申请号：US12346129

申请日：2008-12-30

申请人： Gil Balog

发明人： Gil Balog

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/31707 ,  G01R31/318511

摘要： Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.

公开(公告)号：US20090192754A1

公开(公告)日：2009-07-30

申请号：US12418024

申请日：2009-04-03

申请人： Gil Balog ,  Reed Linde ,  Avi Golan

发明人： Gil Balog ,  Reed Linde ,  Avi Golan

IPC分类号： G01R31/00

CPC分类号： G01R31/2601 ,  G01R31/2894 ,  G01R31/31707 ,  G01R31/3172 ,  G01R31/318511

摘要： Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

摘要翻译： 公开了用于半导体测试的方法和系统。 在一个实施例中，防止测试太慢的设备完成测试，从而允许未测试的设备开始更早测试。

公开(公告)号：US07567947B2

公开(公告)日：2009-07-28

申请号：US11396938

申请日：2006-04-04

申请人： Gil Balog

发明人： Gil Balog

IPC分类号： G06F17/00 ,  G06N5/02

CPC分类号： G01R31/31912 ,  G01R31/318314 ,  G06N5/025

摘要： Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.

摘要翻译： 半导体测试方法和系统。 在一个实施例中，半导体测试方法包括以下阶段中的一个或多个：定义与半导体测试有关的规则，验证规则，将规则与其他规则绑定，将规则与其他规则相关联，发布规则，实现规则 ，并对有关规则采取后续行动。 在一个实施例中，半导体测试系统包括以下模块中的一个或多个：规则创建模块，分析模块，模拟模块，实时生产模块和离线生产模块 ）。 在一个实施例中，用户友好的图形用户界面可用于定义规则的构建块和/或用于查看规则所属的类别的可选层次结构。

公开(公告)号：US07340359B2

公开(公告)日：2008-03-04

申请号：US11343209

申请日：2006-01-31

申请人： Nir Erez ,  Gil Balog

发明人： Nir Erez ,  Gil Balog

IPC分类号： G06F19/00

CPC分类号： G01R31/2894 ,  G01R31/287 ,  G11C29/56 ,  G11C29/56008

摘要： A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and other population(s). The method includes the step of associating test flows to the populations. Each test flow includes stress testing sequence. The stress testing sequence for the quality or reliability fail candidate population includes a stress test of increased duration compared to duration of a stress test in the test flow of the other population. The stress test sequence for the other population includes a stress test of increased voltage compared to corresponding operating voltage specification for a semiconductor unit. The method further includes the step of applying, within a sort testing stage, the corresponding test flow to the populations and identifying any unit which failed the stress sequence.

摘要翻译： 一种用于增加半导体单元的质量或可靠性的方法，包括提供质量或可靠性测试的少数几个半导体单元。 人口不包括质量或可靠性失败的候选人群和其他人口。 该方法包括将测试流与人群相关联的步骤。 每个测试流程包括压力测试序列。 质量或可靠性失败候选人群的压力测试序列包括与其他人群的测试流程中的压力测试持续时间相比持续时间增加的压力测试。 对于其他人群的应力测试序列包括与半导体单元的相应工作电压规格相比增加的电压的应力测试。 该方法还包括在分类测试阶段期间将对应的测试流程应用于群体并识别任何失败应力序列的单元的步骤。