公开(公告)号：US08169022B2

公开(公告)日：2012-05-01

申请号：US12818232

申请日：2010-06-18

申请人： Lin Cheng ,  Michael Mazzola

发明人： Lin Cheng ,  Michael Mazzola

IPC分类号： H01L29/66

CPC分类号： H01L29/8083 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/868 ,  H01L29/872

摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）或二极管，例如结型势垒肖特基（JBS）二极管或PiN二极管。 器件具有通过外延生长形成的渐变p型半导体层和/或区域。 该方法不需要离子注入。 这些器件可以由诸如碳化硅（SiC）的宽带隙半导体材料制成，并且可以用于高温和高功率应用中。

公开(公告)号：US20070228505A1

公开(公告)日：2007-10-04

申请号：US11396615

申请日：2006-04-04

申请人： Michael Mazzola ,  Lin Cheng

发明人： Michael Mazzola ,  Lin Cheng

IPC分类号： H01L31/07

CPC分类号： H01L29/872 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611

摘要： A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p+-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P+ guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.

摘要翻译： 描述了结屏障肖特基（JBS）整流器件及制造器件的方法。 该器件包括外延生长的第一n型漂移层和形成p + S + n结的p型区域和自平面化外延生长的第二n型漂移区之间，并且任选地在 顶级的p型地区。 该装置可以包括边缘终端结构，例如暴露或掩埋的P +保护环，再生长或植入的连接终止延伸（JTE）区域或向下蚀刻到衬底的“深”台面。 与第二n型漂移区的肖特基接触和与p型区的欧姆接触一起用作阳极。 阴极可以通过欧姆接触形成在晶片背面的n型区域上。 该器件可用于单片数字，模拟和微波集成电路。

公开(公告)号：US20070029573A1

公开(公告)日：2007-02-08

申请号：US11198298

申请日：2005-08-08

申请人： Lin Cheng ,  Michael Mazzola

发明人： Lin Cheng ,  Michael Mazzola

IPC分类号： H01L29/423

CPC分类号： H01L29/8083 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66909

摘要： Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以在SiC中实现，并且可以包括外延生长的n型漂移和p型沟槽栅极区域，以及在沟槽p型栅极区域顶部的n型外延再生长沟道区域。 源极区域可以在沟道区域的顶部外延再生长或选择性地植入沟道区域。 然后可以形成到源极，栅极和漏极区域的欧姆接触。 这些装置可以包括边缘终端结构，例如保护环，连接终止扩展（JTE）或其他合适的p-n阻塞结构。 这些器件可以用不同的阈值电压制造，并且可以针对相同沟道掺杂的耗尽和增强的工作模式来实现。 这些器件可用作分立功率晶体管和数字，模拟和单片微波集成电路。

公开(公告)号：US08928074B2

公开(公告)日：2015-01-06

申请号：US13434976

申请日：2012-03-30

申请人： Lin Cheng ,  Michael Mazzola

发明人： Lin Cheng ,  Michael Mazzola

IPC分类号： H01L29/66 ,  H01L29/36 ,  H01L29/872 ,  H01L29/808 ,  H01L29/868 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/8083 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/868 ,  H01L29/872

摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）或二极管，例如结型势垒肖特基（JBS）二极管或PiN二极管。 器件具有通过外延生长形成的渐变p型半导体层和/或区域。 该方法不需要离子注入。 这些器件可以由诸如碳化硅（SiC）的宽带隙半导体材料制成，并且可以用于高温和高功率应用中。

公开(公告)号：US20060160316A1

公开(公告)日：2006-07-20

申请号：US11305337

申请日：2005-12-19

申请人： Jeffrey Casady ,  Michael Mazzola

发明人： Jeffrey Casady ,  Michael Mazzola

IPC分类号： H01L31/0312 ,  H01L21/336 ,  H01L21/00

CPC分类号： H01L29/78603 ,  H01L21/0445 ,  H01L21/7602 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/4908 ,  H01L29/732 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/802 ,  H01L29/812 ,  Y10S438/917 ,  Y10S438/931

摘要： A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.

摘要翻译： 碳化硅半绝缘外延层用于产生与传统器件相比具有显着性能优点的功率器件和集成电路。 在诸如导电衬底的衬底上形成碳化硅半绝缘层，并且在碳化硅半绝缘层上形成一个或多个半导体器件。 包括例如4H或6H碳化硅的碳化硅半绝缘层使用补偿材料形成，补偿材料根据半绝缘层的优选特性来选择。 补偿材料包括例如硼，钒，铬或锗。 使用碳化硅半绝缘层为高功率和高频半导体应用提供绝缘优势和改善的热性能。

公开(公告)号：US20060011924A1

公开(公告)日：2006-01-19

申请号：US11176625

申请日：2005-07-08

申请人： Michael Mazzola ,  Joseph Merrett

发明人： Michael Mazzola ,  Joseph Merrett

IPC分类号： H01L29/15

CPC分类号： H01L29/872 ,  H01L27/0641 ,  H01L27/0814 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/8083

摘要： A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.

摘要翻译： 描述了组合自对准垂直结型场效应晶体管与蚀刻注入栅极和集成反并联肖特基势垒二极管的开关元件。 二极管的阳极在器件级连接到晶体管的源极，以减少杂散电感引起的损耗。 SBD阳极区域中的SiC表面通过干蚀刻进行调理，以实现低肖特基势垒高度，从而降低与SBD的导通电压相关的功率损耗。

公开(公告)号：US07009209B2

公开(公告)日：2006-03-07

申请号：US10033785

申请日：2002-01-03

申请人： Jeffrey B. Casady ,  Michael Mazzola

发明人： Jeffrey B. Casady ,  Michael Mazzola

IPC分类号： H01L31/0312

CPC分类号： H01L29/78603 ,  H01L21/0445 ,  H01L21/7602 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/4908 ,  H01L29/732 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/802 ,  H01L29/812 ,  Y10S438/917 ,  Y10S438/931

摘要： A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.

公开(公告)号：US20080003731A1

公开(公告)日：2008-01-03

申请号：US11808701

申请日：2007-06-12

申请人： Michael Mazzola ,  Joseph Merrett

发明人： Michael Mazzola ,  Joseph Merrett

IPC分类号： H01L21/82

CPC分类号： H01L29/872 ,  H01L27/0641 ,  H01L27/0814 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/8083

摘要： A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.

公开(公告)号：US07432171B2

公开(公告)日：2008-10-07

申请号：US11305337

申请日：2005-12-19

申请人： Jeffrey B. Casady ,  Michael Mazzola

发明人： Jeffrey B. Casady ,  Michael Mazzola

IPC分类号： H01L21/20 ,  H01L21/76

CPC分类号： H01L29/78603 ,  H01L21/0445 ,  H01L21/7602 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/4908 ,  H01L29/732 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/802 ,  H01L29/812 ,  Y10S438/917 ,  Y10S438/931

摘要： A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.

摘要翻译： 碳化硅半绝缘外延层用于产生与传统器件相比具有显着性能优点的功率器件和集成电路。 在诸如导电衬底的衬底上形成碳化硅半绝缘层，并且在碳化硅半绝缘层上形成一个或多个半导体器件。 包括例如4H或6H碳化硅的碳化硅半绝缘层使用补偿材料形成，补偿材料根据半绝缘层的优选特性来选择。 补偿材料包括例如硼，钒，铬或锗。 使用碳化硅半绝缘层为高功率和高频半导体应用提供绝缘优势和改善的热性能。

公开(公告)号：US6119406A

公开(公告)日：2000-09-19

申请号：US213072

申请日：1998-12-16

申请人： Salvatore J. Gulisano ,  Michael Mazzola ,  Stephen C. Ivy ,  Rhys Johnson

发明人： Salvatore J. Gulisano ,  Michael Mazzola ,  Stephen C. Ivy ,  Rhys Johnson

IPC分类号： B60J10/00 ,  B60J10/04 ,  B60R13/02 ,  B60J5/04

CPC分类号： B60R13/0243 ,  B60J10/265 ,  B60J10/75 ,  B60R13/0206

摘要： An automotive door trim panel assembly including a plastic inner panel having a relatively thick, rigid, hollow retaining section which is designed for snap-fit installation of the assembly with a weather seal having a snap-on groove defined therein to thereby eliminate the need for additional fastening hardware while at the same time to provide increased rigidity and ease of tooling. The assembly also includes a contour door trim member for the inner panel.

摘要翻译： 一种汽车门装饰板组件，其包括具有相对较厚，刚性的中空保持部分的塑料内板，其设计成用于具有限定在其中的卡扣槽的气密密封件的组合安装，从而不需要 同时提供额外的紧固硬件，同时提供增加的刚性和易于加工。 组件还包括用于内板的轮廓门装饰件。