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    SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING
    3.
    发明申请
    SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING 审中-公开
    具有复位栅的自对准TRENCH场效应晶体管和带有基极接触区的双极晶体管晶体管和制造方法

    公开(公告)号：US20080061362A1

    公开(公告)日：2008-03-13

    申请号：US11934805

    申请日：2007-11-05

    申请人： Joseph Merrett ,  Igor Sankin

    发明人： Joseph Merrett ,  Igor Sankin

    IPC分类号： H01L29/78 ,  H01L29/732

    CPC分类号： H01L29/66068 ,  H01L29/732 ,  H01L29/808

    摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

    摘要翻译： 描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。 所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。 还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法以及制造这些器件的方法。 半导体器件可以制成碳化硅。

    Self-aligned silicon carbide semiconductor devices and methods of making the same
    4.
    发明申请
    Self-aligned silicon carbide semiconductor devices and methods of making the same 有权
    自对准碳化硅半导体器件及其制造方法

    公开(公告)号：US20050199882A1

    公开(公告)日：2005-09-15

    申请号：US11076857

    申请日：2005-03-11

    申请人： Igor Sankin ,  Janna Casady ,  Joseph Merrett

    发明人： Igor Sankin ,  Janna Casady ,  Joseph Merrett

    IPC分类号： H01L29/15 ,  H01L31/0312

    CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/66863 ,  H01L29/8128

    摘要： A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

    摘要翻译： 描述了具有改善的电流稳定性的自对准碳化硅功率MESFET和制造该器件的方法。 包括由栅极凹槽分开的升高的源极和漏极区域的器件由于即使在低栅极偏置处减小的表面俘获效应也具有改善的电流稳定性。 可以使用自对准工艺来制造器件，其中蚀刻在n掺杂的SiC沟道层上包括n + +掺杂的SiC层的衬底以限定凸起的源极和漏极区域（例如， 使用金属蚀刻掩模。 然后将金属蚀刻掩模退火以形成源极和漏极欧姆接触。 然后生长或沉积单层或多层介电膜并进行各向异性蚀刻。 随后使用蒸发或其他各向异性沉积技术沉积肖特基接触层和最后的金属层，然后对电介质层或层进行任意的各向同性蚀刻。

    SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING
    5.
    发明申请
    SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING 有权
    具有复位栅的自对准TRENCH场效应晶体管和带有基极接触区的双极晶体管晶体管和制造方法

    公开(公告)号：US20070275527A1

    公开(公告)日：2007-11-29

    申请号：US11293261

    申请日：2005-12-05

    申请人： Joseph Merrett ,  Igor Sankin

    发明人： Joseph Merrett ,  Igor Sankin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66068 ,  H01L29/732 ,  H01L29/808

    摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

    摘要翻译： 描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。 所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。 还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法以及制造这些器件的方法。 半导体器件可以制成碳化硅。

    Self-aligned silicon carbide semiconductor devices and methods of making the same
    8.
    发明申请
    Self-aligned silicon carbide semiconductor devices and methods of making the same 有权
    自对准碳化硅半导体器件及其制造方法

    公开(公告)号：US20070122951A1

    公开(公告)日：2007-05-31

    申请号：US11699509

    申请日：2007-01-30

    申请人： Igor Sankin ,  Janna Casady ,  Joseph Merrett

    发明人： Igor Sankin ,  Janna Casady ,  Joseph Merrett

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/66863 ,  H01L29/8128

    摘要： A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

    摘要翻译： 描述了具有改善的电流稳定性的自对准碳化硅功率MESFET和制造该器件的方法。 包括由栅极凹槽分开的升高的源极和漏极区域的器件由于即使在低栅极偏置处减小的表面俘获效应也具有改善的电流稳定性。 可以使用自对准工艺来制造器件，其中蚀刻在n掺杂的SiC沟道层上包括n + +掺杂的SiC层的衬底以限定凸起的源极和漏极区域（例如， 使用金属蚀刻掩模。 然后将金属蚀刻掩模退火以形成源极和漏极欧姆接触。 然后生长或沉积单层或多层介电膜并进行各向异性蚀刻。 随后使用蒸发或其他各向异性沉积技术沉积肖特基接触层和最后的金属层，然后对电介质层或层进行任意的各向同性蚀刻。