Amplifier for alternating signals superimposed on a continuous signal and method for amplifying such signals
    1.
    发明授权
    Amplifier for alternating signals superimposed on a continuous signal and method for amplifying such signals 失效
    用于叠加在连续信号上的交替信号的放大器和用于放大这种信号的方法

    公开(公告)号:US06876253B2

    公开(公告)日:2005-04-05

    申请号:US10254227

    申请日:2002-09-25

    CPC classification number: H03F3/45928 G11B5/02 G11B2005/0016

    Abstract: This amplifier is intended for amplifying variable signals superimposed on a continuous signal. This continuous signal serves in particular for biasing a component, a magnetoresistive resistor used as a hard disk reading head. To avoid the harmful effects of a sudden fluctuation in the continuous signal, this amplifier comprises a set of switchable reactive elements (70) for acting on said transfer function and a bias drift compensation circuit (80) for controlling the switching of said switchable elements with a view to anticipating the effects of said fluctuation.

    Abstract translation: 该放大器用于放大叠加在连续信号上的可变信号。 该连续信号特别用于偏置组件,用作硬盘读取头的磁阻电阻器。 为了避免连续信号中的突然波动的有害影响,该放大器包括用于作用于所述传递函数的一组可切换无功元件(70)和用于控制所述可切换元件的切换的偏置漂移补偿电路(80) 以期预测所述波动的影响。

    Eight-shaped RF balun
    2.
    发明授权
    Eight-shaped RF balun 有权
    八形射频平衡 - 不平衡转换器

    公开(公告)号:US08427388B2

    公开(公告)日:2013-04-23

    申请号:US12953138

    申请日:2010-11-23

    Abstract: Symmetrical eight-shaped balun (BALanced-to-UNbalanced converter) comprising a first and second eye, each eye comprising conducting tracks forming turns. The eyes comprise an equal number of primary turns that form a first conducting path from a first terminal to a second terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. Moreover, the eyes further comprise an equal number of secondary turns that form a second conducting path from a third terminal to a fourth terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. The geometrical and electrical middle points of primary and secondary turns are all superposed and further are located in the same plane.

    Abstract translation: 包括第一眼和第二眼的对称八角平衡 - 不平衡转换器(平衡到不平衡转换器),每只眼睛包括形成转弯的导轨。 眼睛包括形成从第一端子到第二端子的第一导电路径的相等数量的初级匝,其中在工作中电流在第一眼睛中的第一方向和第二眼睛中的第二方向上流动。 此外,眼睛还包括相等数量的次级匝,其形成从第三端子到第四端子的第二导电路径,其中在工作中电流在第一眼睛中沿第一方向流动,在第二方向上在第二端子中流动 眼。 初级和次级匝的几何和电中点全部叠加,并进一步位于同一平面。

    Circuit for providing a logic gate function and a latch function
    3.
    发明申请
    Circuit for providing a logic gate function and a latch function 有权
    提供逻辑门功能和锁存功能的电路

    公开(公告)号:US20060279337A1

    公开(公告)日:2006-12-14

    申请号:US10572612

    申请日:2004-09-10

    Applicant: Lionel Guiraud

    Inventor: Lionel Guiraud

    CPC classification number: H03K19/212 H03K19/086

    Abstract: The invention relates to an electronic circuit comprising differential signal input means, a combining stage, a discriminating stage and differential signal output means. The discriminating stage comprises four transistors (Q8, Q9, Q10, Q11) each having first electrodes (83, 93, 103, 113) and second electrodes (81, 91, 101, 111) and a respective gate electrode (82, 92, 102, 112). The first electrodes of said four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of said four transistors respectively.

    Abstract translation: 本发明涉及一种包括差分信号输入装置,组合级,识别级和差分信号输出装置的电子电路。 鉴别级包括四个晶体管(Q 8,Q 9,Q 10,Q 11),每个具有第一电极(83,93,103,113)和第二电极(81,91,101,111)和相应的栅电极 82,92,102,112)。 所述四个晶体管的第一电极被连接到公共节点。 组合级被布置成将差分输入信号转换成分别施加到所述四个晶体管中的一些的栅电极的栅极信号。

    EIGHT-SHAPED RF BALUN
    4.
    发明申请

    公开(公告)号:US20110148733A1

    公开(公告)日:2011-06-23

    申请号:US12953138

    申请日:2010-11-23

    Abstract: Symmetrical eight-shaped balun (BALanced-to-UNbalanced converter) comprising a first and second eye, each eye comprising conducting tracks forming turns. The eyes comprise an equal number of primary turns that form a first conducting path from a first terminal to a second terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. Moreover, the eyes further comprise an equal number of secondary turns that form a second conducting path from a third terminal to a fourth terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. The geometrical and electrical middle points of primary and secondary turns are all superposed and further are located in the same plane.

    Abstract translation: 包括第一眼和第二眼的对称八角平衡 - 不平衡转换器(平衡到不平衡转换器),每只眼睛包括形成转弯的导轨。 眼睛包括形成从第一端子到第二端子的第一导电路径的相等数量的初级匝,其中在工作中电流在第一眼睛中的第一方向和第二眼睛中的第二方向上流动。 此外,眼睛还包括相等数量的次级匝,其形成从第三端子到第四端子的第二导电路径,其中在工作中电流在第一眼睛中沿第一方向流动,在第二方向上在第二端子中流动 眼。 初级和次级匝的几何和电中点全部叠加,并进一步位于同一平面。

    ELECTRIC DEVICE COMPRISING AN IMPROVED ELECTRODE
    5.
    发明申请
    ELECTRIC DEVICE COMPRISING AN IMPROVED ELECTRODE 有权
    包含改进电极的电气设备

    公开(公告)号:US20100230787A1

    公开(公告)日:2010-09-16

    申请号:US12299325

    申请日:2007-04-30

    Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.

    Abstract translation: 本发明涉及一种包括电气元件的电气设备,电气元件包括具有第一表面(106)和柱(108)的第一电极(104),该柱从第一表面沿第一方向(110)延伸, ,所述柱具有从所述第一表面平行于所述第一方向测量的长度,所述柱具有垂直于所述第一方向的横截面(116),所述柱具有封闭所述柱并且沿所述第一方向延伸的侧壁表面(120) 其特征在于,所述支柱包括沿柱的长度的至少一部分延伸的刻痕(124)和突起(122)中的任何一个,以提供支柱(108)改善的机械稳定性。 电极允许以成本有效的方式制造诸如电容器,储能装置或二极管的电气元件,具有改进的性能。

    Circuit for providing a logic gate function and a latch function
    6.
    发明授权
    Circuit for providing a logic gate function and a latch function 有权
    提供逻辑门功能和锁存功能的电路

    公开(公告)号:US07250790B2

    公开(公告)日:2007-07-31

    申请号:US10572612

    申请日:2004-09-10

    Applicant: Lionel Guiraud

    Inventor: Lionel Guiraud

    CPC classification number: H03K19/212 H03K19/086

    Abstract: An electronic circuit for providing a logic gate function includes a differential signal input, a combining stage, a discriminating stage and a differential signal output. The discriminating stage includes four transistors each having first electrodes and second electrodes and a respective gate electrode. The first electrodes of the four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of the four transistors respectively.

    Abstract translation: 用于提供逻辑门功能的电子电路包括差分信号输入,组合级,判别级和差分信号输出。 鉴别级包括四个晶体管,每个具有第一电极和第二电极以及相应的栅电极。 四个晶体管的第一电极连接到公共节点。 组合级被布置成将差分输入信号转换成分别施加到四个晶体管中的一些的栅电极的栅极信号。

    Source or emitter follower buffer circuit and method

    公开(公告)号:US09654057B2

    公开(公告)日:2017-05-16

    申请号:US13431505

    申请日:2012-03-27

    CPC classification number: H03F1/086 H03F1/083 H03F3/505

    Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained.In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

    Electronic device having electrode with high area density and improved mechanical stability
    9.
    发明授权
    Electronic device having electrode with high area density and improved mechanical stability 有权
    具有电极面积密度高,机械稳定性好的电子器件

    公开(公告)号:US08283750B2

    公开(公告)日:2012-10-09

    申请号:US12299325

    申请日:2007-04-30

    Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.

    Abstract translation: 本发明涉及一种包括电气元件的电气设备,电气元件包括具有第一表面(106)和柱(108)的第一电极(104),该柱从第一表面沿第一方向(110)延伸, ,所述柱具有从所述第一表面平行于所述第一方向测量的长度,所述柱具有垂直于所述第一方向的横截面(116),所述柱具有封闭所述柱并且沿所述第一方向延伸的侧壁表面(120) 其特征在于,所述支柱包括沿柱的长度的至少一部分延伸的刻痕(124)和突起(122)中的任何一个,以提供支柱(108)改善的机械稳定性。 电极允许以成本有效的方式制造诸如电容器,储能装置或二极管的电气元件,具有改进的性能。

    Source or Emitter Follower Buffer Circuit and Method
    10.
    发明申请
    Source or Emitter Follower Buffer Circuit and Method 有权
    源或发射器跟随器缓冲电路和方法

    公开(公告)号:US20120249191A1

    公开(公告)日:2012-10-04

    申请号:US13431505

    申请日:2012-03-27

    CPC classification number: H03F1/086 H03F1/083 H03F3/505

    Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained.In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

    Abstract translation: 一方面,缓冲电路包括源极或射极跟随器输入级和输出级。 在级之间提供负载,其包括缓冲电路的输出负载的表示。 这提高了电路线性度,同时实现了高输入阻抗。 在另一方面,缓冲电路包括源极或射极跟随器输出级。 提供了滤波器形式的负载,其包括缓冲电路的输出负载的表示。

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