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1.发明申请公开(公告)号：US20090094446A1
公开(公告)日：2009-04-09
申请号：US12277365
申请日：2008-11-25
IPC分类号： G06F15/177
CPC分类号： G06F1/206
摘要： A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
摘要翻译： 一种用于根据存储在集成电路的非易失性存储器中的信息自动初始化系统的操作设置的方法，使得当系统运行时系统满足可能是微处理器的集成电路的操作要求 。 在制造测试期间，集成电路的环境要求被确定并存储在集成电路的非易失性存储器内。 在系统初始化期间，从集成电路读取的测试值确定所需的工作电压，频率和冷却要求等环境控制值。 这些值由系统的接口从集成电路的接口读取。 系统设置由值控制以提供所需的操作环境，并且可以在系统内捕获值以用于后续操作和初始化序列。
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2.发明授权Integrated circuit environment initialization according to information stored within the integrated circuit 失效根据存储在集成电路内的信息，集成电路环境初始化公开(公告)号：US07996693B2
公开(公告)日：2011-08-09
申请号：US12277365
申请日：2008-11-25
IPC分类号： G06F1/26
CPC分类号： G06F1/206
摘要： A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
摘要翻译： 一种用于根据存储在集成电路的非易失性存储器中的信息自动初始化系统的操作设置的方法，使得当系统运行时系统满足可能是微处理器的集成电路的操作要求 。 在制造测试期间，集成电路的环境要求被确定并存储在集成电路的非易失性存储器中。 在系统初始化期间，从集成电路读取的测试值确定所需的工作电压，频率和冷却要求等环境控制值。 这些值由系统的接口从集成电路的接口读取。 系统设置由值控制以提供所需的操作环境，并且可以在系统内捕获值以用于后续操作和初始化序列。
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3.发明授权公开(公告)号：US07472297B2
公开(公告)日：2008-12-30
申请号：US11304956
申请日：2005-12-15
IPC分类号： G06F1/26
CPC分类号： G06F1/206
摘要： A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
摘要翻译： 一种用于根据存储在集成电路的非易失性存储器中的信息自动初始化系统的操作设置的方法，使得当系统运行时系统满足可能是微处理器的集成电路的操作要求 。 在制造测试期间，集成电路的环境要求被确定并存储在集成电路的非易失性存储器中。 在系统初始化期间，从集成电路读取的测试值确定所需的工作电压，频率和冷却要求等环境控制值。 这些值由系统的接口从集成电路的接口读取。 系统设置由值控制以提供所需的操作环境，并且可以在系统内捕获值以用于后续操作和初始化序列。
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4.发明授权Multicore processor and method of use that adapts core functions based on workload execution 有权基于工作负载执行的多核处理器和使用方法可以调整核心功能公开(公告)号：US08327126B2
公开(公告)日：2012-12-04
申请号：US12197357
申请日：2008-08-25
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。
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5.发明授权Optimizing execution of single-threaded programs on a multiprocessor managed by compilation 有权在编译器管理的多处理器上优化单线程程序的执行公开(公告)号：US08312455B2
公开(公告)日：2012-11-13
申请号：US11960021
申请日：2007-12-19
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译： 一种用于优化多核处理器上单个线程程序的执行的方法。 该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以供所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。
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6.发明申请Optimizing Execution of Single-Threaded Programs on a Multiprocessor Managed by Compilation 有权通过编译管理的多处理器上优化单线程程序的执行公开(公告)号：US20090164755A1
公开(公告)日：2009-06-25
申请号：US11960021
申请日：2007-12-19
IPC分类号： G06F9/312
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译： 一种用于优化多核处理器上单个线程程序的执行的方法。 该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以由所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。
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7.发明授权Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution 有权通过对单线程程序执行前瞻性操作来在执行之前识别多条指令线程来并行化单线程程序公开(公告)号：US08495636B2
公开(公告)日：2013-07-23
申请号：US11959906
申请日：2007-12-19
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译： 一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令， 并分配空闲核心以执行推测性指令。
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公开(公告)号：US08379847B2
公开(公告)日：2013-02-19
申请号：US12828080
申请日：2010-06-30
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译： 设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据 由密钥定义的加密顺序。 加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。
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9.发明授权System and method to optimize multi-core microprocessor performance using voltage offsets 失效使用电压补偿优化多核微处理器性能的系统和方法公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。
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10.发明授权Method and apparatus for controlling heat generation in a multi-core processor 有权用于控制多核处理器中的发热的方法和装置公开(公告)号：US07617403B2
公开(公告)日：2009-11-10
申请号：US11459988
申请日：2006-07-26
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.
摘要翻译： 所公开的方法和装置可以减少多核处理器中的发热。 在一个实施例中，多核处理器随着时间跨越处理器管芯以预定模式关闭所选择的处理器核，以减少处理器的平均发热量。 所公开的多核处理器可以减少或避免影响处理器寿命的不期望的热点。
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