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公开(公告)号：US07930129B2
公开(公告)日：2011-04-19
申请号：US12114032
申请日：2008-05-02
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。
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2.发明授权System and method to optimize multi-core microprocessor performance using voltage offsets 失效使用电压补偿优化多核微处理器性能的系统和方法公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。
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公开(公告)号：US07389195B2
公开(公告)日：2008-06-17
申请号：US11278303
申请日：2006-03-31
IPC分类号： G01R31/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。
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4.发明申请System and Method to Optimize Multi-Core Microprocessor Performance Using Voltage Offsets 失效使用电压偏移优化多核微处理器性能的系统和方法公开(公告)号：US20080052542A1
公开(公告)日：2008-02-28
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。
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公开(公告)号：US20080234955A1
公开(公告)日：2008-09-25
申请号：US12114032
申请日：2008-05-02
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。
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公开(公告)号：US07667470B2
公开(公告)日：2010-02-23
申请号：US12143911
申请日：2008-06-23
申请人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , H01L23/50 , H01L2924/0002 , Y02D10/172 , H01L2924/00
摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。
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公开(公告)号：US20080252308A1
公开(公告)日：2008-10-16
申请号：US12143911
申请日：2008-06-23
申请人： Jean Audet , Louis B. Capps , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G01R31/26
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , H01L23/50 , H01L2924/0002 , Y02D10/172 , H01L2924/00
摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。
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公开(公告)号：US07420378B2
公开(公告)日：2008-09-02
申请号：US11456658
申请日：2006-07-11
申请人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , H01L23/50 , H01L2924/0002 , Y02D10/172 , H01L2924/00
摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。
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9.发明申请公开(公告)号：US20080012583A1
公开(公告)日：2008-01-17
申请号：US11456658
申请日：2006-07-11
申请人： JEAN AUDET , Louis B. Capps , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： JEAN AUDET , Louis B. Capps , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , H01L23/50 , H01L2924/0002 , Y02D10/172 , H01L2924/00
摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。
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10.发明授权Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip 失效在多核微处理器集成电路芯片上定制化核心的装置和方法公开(公告)号：US07268570B1
公开(公告)日：2007-09-11
申请号：US11426646
申请日：2006-06-27
申请人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Joanne Ferris , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G01R31/02
CPC分类号： G01R31/2855
摘要： An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.
摘要翻译： 一种用于提供多核集成电路芯片的装置和方法，其降低了封装和板的成本，同时优化用于单个电压平面的芯的性能。 说明性实施例的装置和方法使用动态老化技术，其优化芯片上的所有核心以在单个电压下以峰值性能运行。 每个核心都具有定制的老化电压，可在整个芯片上提供均匀的功率和性能。 这导致集成电路芯片中更高的老化成本和更低的总功率。 通过使用负偏置温度不稳定性影响由所施加的老化电压施加的磁芯，可以实现在单电压下以峰值性能运行的磁芯的优化。
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