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公开(公告)号：US07283410B2
公开(公告)日：2007-10-16
申请号：US11308215
申请日：2006-03-13
IPC分类号： G11C7/00
CPC分类号： G11C11/4125
摘要： A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.
摘要翻译： 一种用于自动调整存储器件（例如SRAM阵列）中的一个或多个电参数的系统和方法。 该系统和方法实现SRAM感测子阵列，用于加速收集故障率数据，用于确定单个事件不起作息和主SRAM阵列性能之间的最佳权衡的操作点。 将加速失败率数据输入到在电离粒子环境中将初级SRAM存储器阵列的SEU灵敏度设定为预定故障率的算法。 为了提供符合最佳性能的SEU的免疫力，实时地维持预定的故障率。
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公开(公告)号：US07572682B2
公开(公告)日：2009-08-11
申请号：US11755995
申请日：2007-05-31
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译： 提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。 小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。 保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。 抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层 第一厚度位于第一扩散阻挡层上。
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公开(公告)号：US07381594B2
公开(公告)日：2008-06-03
申请号：US11290890
申请日：2005-11-30
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/336 , H01L21/331
CPC分类号： H01L23/5256 , H01L21/268 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.
摘要翻译： 提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。 根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。 本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。
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公开(公告)号：US20080296728A1
公开(公告)日：2008-12-04
申请号：US11755995
申请日：2007-05-31
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译： 提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。 小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。 保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。 抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层 第一厚度位于第一扩散阻挡层上。
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5.发明授权Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上公开(公告)号：US07545253B2
公开(公告)日：2009-06-09
申请号：US12128100
申请日：2008-05-28
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。
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6.发明授权公开(公告)号：US07518191B1
公开(公告)日：2009-04-14
申请号：US12173280
申请日：2008-07-15
IPC分类号： H01L29/00
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7835 , H01L29/78618
摘要： Silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a semiconductor device comprises: a gate conductor spaced above a semiconductor layer by a gate dielectric; dielectric spacers disposed laterally adjacent to sidewalls of the gate conductor; source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and a conductive implant region comprising metallic species disposed in a bottom region of the semiconductor layer for electrically connecting the source junction to the body region, wherein a drain-side of the implant region is spaced apart from the body region and a source-side of the implant region contacts the body region.
摘要翻译： 描述了具有身体绑定到源的绝缘体上硅器件。 在一个实施例中，半导体器件包括：通过栅极电介质在半导体层之上间隔开的栅极导体; 电介质间隔件设置成横向邻近门导体的侧壁; 源极和漏极结，其横向间隔开半导体层中的体区; 以及导电植入区域，其包括设置在所述半导体层的底部区域中的金属物质，用于将所述源极接头与所述体区域电连接，其中所述植入区域的漏极侧与所述体区域间隔开，并且源极侧 植入区域接触身体区域。
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7.发明授权Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上公开(公告)号：US07460003B2
公开(公告)日：2008-12-02
申请号：US11372387
申请日：2006-03-09
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。
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8.发明授权公开(公告)号：US07442614B1
公开(公告)日：2008-10-28
申请号：US12052807
申请日：2008-03-21
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7835 , H01L29/78618
摘要： Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer by a gate dielectric, dielectric sidewall spacers adjacent to sidewalls of the gate conductor, and source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and implanting metallic species in a bottom region of the semiconductor layer to form a conductive implant region to electrically connect the source junction to the body region.
摘要翻译： 描述了具有身体绑定到源的绝缘体上的硅的制造方法。 在一个实施例中，一种形成晶体管器件的方法包括：提供包括通过栅极电介质在半导体层之上间隔开的栅极导体的半导体形貌，与栅极导体的侧壁相邻的电介质侧壁间隔和横向间隔开的源极和漏极结 通过半导体层中的体区; 以及将所述金属物质植入所述半导体层的底部区域中以形成导电注入区域，以将所述源极结电连接到所述身体区域。
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9.发明申请Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开具有伪装配置的存储元件及其使用方法公开(公告)号：US20080067600A1
公开(公告)日：2008-03-20
申请号：US11533191
申请日：2006-09-19
IPC分类号： H01L23/62
CPC分类号： H01L23/585 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。 提供了许多其他方面。
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10.发明申请ELECTRONIC FUSE WITH CONFORMAL FUSE ELEMENT FORMED OVER A FREESTANDING DIELECTRIC SPACER 失效具有合适的保险丝元件的电子保险丝在自动电介质间隔件上形成公开(公告)号：US20080258857A1
公开(公告)日：2008-10-23
申请号：US12128100
申请日：2008-05-28
IPC分类号： H01H85/08
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。
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