公开(公告)号：US08400197B2

公开(公告)日：2013-03-19

申请号：US13191329

申请日：2011-07-26

申请人： Luca Romano ,  Alessandro Venca ,  Stefano Dal Toso ,  Antonio Milani ,  Brian Brunn

发明人： Luca Romano ,  Alessandro Venca ,  Stefano Dal Toso ,  Antonio Milani ,  Brian Brunn

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0816 ,  H03L7/16 ,  H03L7/1976

摘要： In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.

公开(公告)号：US20120025880A1

公开(公告)日：2012-02-02

申请号：US13191329

申请日：2011-07-26

申请人： Luca Romano ,  Alessandro Venca ,  Stefano Dal Toso ,  Antonio Milani ,  Brian Brunn

发明人： Luca Romano ,  Alessandro Venca ,  Stefano Dal Toso ,  Antonio Milani ,  Brian Brunn

IPC分类号： H03L7/08

CPC分类号： H03L7/08 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0816 ,  H03L7/16 ,  H03L7/1976

摘要： In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.

摘要翻译： 在一个实施例中，一种装置包括被配置为接收参考时钟的抖动发生器; 将抖动添加到参考时钟; 并将包含抖动的参考时钟输出到锁相环（PLL）。 PLL用于为收发器产生本地振荡器（LO）信号。 抖动控制器向抖动发生器输出信号，以控制添加到参考时钟的抖动特性。 具有增加的抖动的参考时钟用于减少由耦合到PLL的射频（RF）攻击者引起的分数杂散。

公开(公告)号：US08421542B2

公开(公告)日：2013-04-16

申请号：US13104404

申请日：2011-05-10

申请人： Luca Romano ,  Randy Tsang

发明人： Luca Romano ,  Randy Tsang

IPC分类号： H03L7/08

CPC分类号： H03L7/099 ,  H03J2200/10 ,  H03L7/085 ,  H03L7/103 ,  H03L7/12 ,  H03L2207/06

摘要： Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.