公开(公告)号：US20250078893A1

公开(公告)日：2025-03-06

申请号：US18240852

申请日：2023-08-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying LEE ,  Teng-Hao YEH ,  Wei-Chen CHEN ,  Rachit DOBHAL ,  Zefu ZHAO ,  Chee-Wee LIU

IPC: G11C11/22 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

公开(公告)号：US20250133745A1

公开(公告)日：2025-04-24

申请号：US18489078

申请日：2023-10-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying LEE ,  Ming-Hsiu LEE ,  Zefu ZHAO ,  Chee-Wee LIU

IPC: H10B53/30 ,  H01L21/28 ,  H01L23/522 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

Abstract: A non-volatile memory cell includes a capacitor which includes a top electrode, a bottom electrode, a ferroelectric layer disposed between the top electrode and the bottom electrode, and an amorphous layer disposed between the top electrode and the bottom electrode, wherein an atomic arrangement of the amorphous layer is different from an atomic arrangement of the top electrode and the bottom electrode. A method of fabricating a non-volatile memory cell and a memory cell array thereof are also disclosed.