公开(公告)号：US20220068957A1

公开(公告)日：2022-03-03

申请号：US17009968

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Chih-Wei HU ,  Hang-Ting LUE ,  Guan-Ru LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

公开(公告)号：US20200243556A1

公开(公告)日：2020-07-30

申请号：US16257176

申请日：2019-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru LEE

IPC: H01L27/11582 ,  H01L21/28

Abstract: A three-dimensional stacked semiconductor device includes a patterned multi-layered stacks formed in an array area of a substrate, wherein one of the patterned multi-layered stacks includes insulating layers and conductive layers arranged alternately, and a top gate layer is disposed above the conductive layers; a vertical channel structure disposed between the patterned multi-layered stacks and comprising a tunneling layer on the patterned multi-layered stacks and a channeling layer on the tunneling layer, wherein lateral sides of the top gate layer of one patterned multi-layered stack directly contact the tunneling layer; and discrete confined structures formed in recess regions adjacent to sidewalls of the conductive layers of the patterned multi-layered stacks, wherein one discrete confined structure includes a blocking layer formed as a liner in the recess region and a charge chapping element in contact with the blocking layer and the tunneling layer.

公开(公告)号：US20220165746A1

公开(公告)日：2022-05-26

申请号：US17102563

申请日：2020-11-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru LEE

IPC: H01L27/11582 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11565

Abstract: A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.