公开(公告)号：US20220068957A1

公开(公告)日：2022-03-03

申请号：US17009968

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Chih-Wei HU ,  Hang-Ting LUE ,  Guan-Ru LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

公开(公告)号：US20210242228A1

公开(公告)日：2021-08-05

申请号：US16782953

申请日：2020-02-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH ,  Yu-Wei JIANG

IPC: H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad.

公开(公告)号：US20210143170A1

公开(公告)日：2021-05-13

申请号：US16680626

申请日：2019-11-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Chih-Wei HU ,  Jia-Rong CHIOU

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device and a method for manufacturing the same are provided. A memory device includes a drain pillar structure, a source pillar structure, a charge trapping structure, a vertical channel structure and a gate structure. The drain pillar structure is formed in a first opening. The source pillar structure is formed in a second opening. The vertical channel structure and the vertical channel structure are formed in a hole partially overlapping the first opening and the second opening. The vertical channel structure is divided into two arc channel parts by the drain pillar structure and the source pillar structure. The gate structure surrounds the drain pillar structure, the source pillar structure and the vertical channel structure.

公开(公告)号：US20150179575A1

公开(公告)日：2015-06-25

申请号：US14617420

申请日：2015-02-09

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L23/535 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/41766 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Abstract translation: 一种器件包括具有凹陷的基底，具有底部和侧面，从基底的上表面延伸到基底中。 侧面包括横向彼此定向的第一和第二侧面。 交替的有源绝缘层和绝缘层的堆叠覆盖在衬底的表面和凹部上。 活性层中的至少一些具有分别在上表面和下平面上方并且大体上平行于上表面和底部延伸的上部和下部。 有源层具有沿着第一和第二侧定位的第一和第二向上延伸，以从它们各自的有源层的下部延伸。 导电带邻接所述有源层的第二向上延伸。 导电条可以包括在第二向上延伸部分的侧面上的侧壁间隔物，导电条通过层间导体连接到覆盖的导体。

公开(公告)号：US20220020761A1

公开(公告)日：2022-01-20

申请号：US16931598

申请日：2020-07-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

公开(公告)号：US20210159243A1

公开(公告)日：2021-05-27

申请号：US16693507

申请日：2019-11-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

公开(公告)号：US20200328154A1

公开(公告)日：2020-10-15

申请号：US16380040

申请日：2019-04-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Kuo-Pin CHANG ,  Chih-Wei HU

IPC: H01L23/528 ,  H01L21/768 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/28 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582

Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

公开(公告)号：US20200243555A1

公开(公告)日：2020-07-30

申请号：US16257165

申请日：2019-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28

Abstract: A memory device and a manufacturing method for the same are provided. The memory device comprises a stack structure and a channel structure. The stack structure is on a substrate and comprises gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrodes, and is on sidewall surfaces of the gate electrodes. The channel structure comprises a first channel structure and a second channel structure. The second channel structure is on an upper surface of the first channel structure. The first channel structure and/or the second channel structure has a ring shape.

公开(公告)号：US20220181347A1

公开(公告)日：2022-06-09

申请号：US17113190

申请日：2020-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH

IPC: H01L27/11582 ,  H01L21/768 ,  G11C16/08

Abstract: A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.

公开(公告)号：US20250107110A1

公开(公告)日：2025-03-27

申请号：US18471292

申请日：2023-09-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU ,  Cheng-Yu LEE

IPC: H10B99/00

Abstract: Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.