公开(公告)号：US20160035425A1

公开(公告)日：2016-02-04

申请号：US14447208

申请日：2014-07-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Ping-Hung Tsai ,  Wen-Jer Tsai

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A programming method for a memory device is provided. The memory device includes a first transistor, a memory cell string, and a second transistor which are electrically connected in series. The memory cell string includes a target memory cell, first and second peripheral memory cells adjacent to the target memory cell, and a plurality of non-target memory cells which are not adjacent to the target memory cell. The programming method includes following steps. The first transistor is turned on, and the second transistor is turned off. A pass voltage is applied to turn on the non-target memory cells, and an assistant voltage is applied to turn on the first and second peripheral memory cells. A programming voltage is applied to program the target memory cell. The assistant voltage is greater than the pass voltage and is less than the programming voltage.

Abstract translation: 提供了一种用于存储器件的编程方法。 存储器件包括串联电连接的第一晶体管，存储单元串和第二晶体管。 存储单元串包括目标存储单元，与目标存储单元相邻的第一和第二外围存储器单元以及与目标存储单元不相邻的多个非目标存储单元。 编程方法包括以下步骤。 第一晶体管导通，第二晶体管截止。 施加通过电压以接通非目标存储器单元，并施加辅助电压以接通第一和第二外围存储器单元。 应用编程电压来对目标存储单元进行编程。 辅助电压大于通过电压，小于编程电压。

公开(公告)号：US20140239370A1

公开(公告)日：2014-08-28

申请号：US13774449

申请日：2013-02-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Guei Yan ,  Wen-Jer Tsai ,  Ping-Hung Tsai

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

Abstract: Provided is a memory device including a first dielectric layer, a T-shaped gate, two charge storage layers and two second dielectric layers. The first dielectric layer is disposed on a substrate. The T-shaped gate is disposed on the first dielectric layer and has an upper gate and a lower gate, wherein two gaps are present respectively at both sides of the lower gate and between the upper gate and the substrate. The charge storage layers are respectively embedded into the gaps. A second dielectric layer is disposed between each charge storage layer and the upper gate, between each charge storage layer and the lower gate and between each charge storage layer and the substrate.

Abstract translation: 提供了包括第一介电层，T形栅极，两个电荷存储层和两个第二电介质层的存储器件。 第一电介质层设置在基板上。 T形栅极设置在第一介电层上并具有上栅极和下栅极，其中两个间隙分别存在于下栅极的两侧以及上栅极和衬底之间。 电荷存储层分别嵌入到间隙中。 在每个电荷存储层和上部栅极之间，在每个电荷存储层和下部栅极之间以及每个电荷存储层和衬底之间设置第二介电层。

公开(公告)号：US08952440B2

公开(公告)日：2015-02-10

申请号：US13774449

申请日：2013-02-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Guei Yan ,  Wen-Jer Tsai ,  Ping-Hung Tsai

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

Abstract: Provided is a memory device including a first dielectric layer, a T-shaped gate, two charge storage layers and two second dielectric layers. The first dielectric layer is disposed on a substrate. The T-shaped gate is disposed on the first dielectric layer and has an upper gate and a lower gate, wherein two gaps are present respectively at both sides of the lower gate and between the upper gate and the substrate. The charge storage layers are respectively embedded into the gaps. A second dielectric layer is disposed between each charge storage layer and the upper gate, between each charge storage layer and the lower gate and between each charge storage layer and the substrate.

Abstract translation: 提供了包括第一介电层，T形栅极，两个电荷存储层和两个第二电介质层的存储器件。 第一电介质层设置在基板上。 T形栅极设置在第一介电层上并具有上栅极和下栅极，其中两个间隙分别存在于下栅极的两侧以及上栅极和衬底之间。 电荷存储层分别嵌入到间隙中。 在每个电荷存储层和上部栅极之间，在每个电荷存储层和下部栅极之间以及每个电荷存储层和衬底之间设置第二介电层。