公开(公告)号：US20200319803A1

公开(公告)日：2020-10-08

申请号：US16742811

申请日：2020-01-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Wang ,  Ping-Hsien Lin ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G06F16/901 ,  G06F12/10

Abstract: A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.

公开(公告)号：US20190073136A1

公开(公告)日：2019-03-07

申请号：US15696325

申请日：2017-09-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Tse-Yuan Wang ,  Che-Wei Tsao ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06

Abstract: A memory controlling method, a memory controlling circuit and a memory system are provided. A memory includes a plurality of memory chips. The memory controlling method includes the following steps: The memory chips are grouped into at least two partner groups by a grouping unit. A quantity of the memory chips in each of the partner groups is at least two. At least one of the memory chips in each of the partner groups is required to serve a reading request or a writing request by a processing unit.

公开(公告)号：US11354123B2

公开(公告)日：2022-06-07

申请号：US17026347

申请日：2020-09-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Han-Wen Hu ,  Yueh-Han Wu ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F7/544 ,  G06F9/345 ,  G06F9/30

Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.

公开(公告)号：US12056361B2

公开(公告)日：2024-08-06

申请号：US17814888

申请日：2022-07-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Wang ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0644 ,  G06F3/0679

Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

公开(公告)号：US11042308B2

公开(公告)日：2021-06-22

申请号：US16742811

申请日：2020-01-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Wang ,  Ping-Hsien Lin ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G06F16/901 ,  G06F12/10

Abstract: A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.