公开(公告)号：US20240234339A9

公开(公告)日：2024-07-11

申请号：US17972953

申请日：2022-10-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11556 ,  H01L27/11582

Abstract: The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.

公开(公告)号：US20230413552A1

公开(公告)日：2023-12-21

申请号：US17845601

申请日：2022-06-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Teng Hao Yeh ,  Cheng-Yu Lee ,  Wei-Chen Chen

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L23/535

Abstract: A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

公开(公告)号：US20230217655A1

公开(公告)日：2023-07-06

申请号：US17570172

申请日：2022-01-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along a first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.

公开(公告)号：US12200933B2

公开(公告)日：2025-01-14

申请号：US17570172

申请日：2022-01-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC: H10B43/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along a first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.

公开(公告)号：US20240136305A1

公开(公告)日：2024-04-25

申请号：US17972953

申请日：2022-10-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11556 ,  H01L27/11582

Abstract: The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.