公开(公告)号：US20240221855A1

公开(公告)日：2024-07-04

申请号：US18149676

申请日：2023-01-04

Applicant: MACRONIX International Co, Ltd.

Inventor： Chih-Wei Hu ,  Teng Hao Yeh ,  Hang-Ting Lue

IPC: G11C29/12 ,  G11C16/26

CPC classification number: G11C29/1201 ,  G11C16/26 ,  G11C2029/1204

Abstract: A memory device and a test method thereof are provided. The memory device (e.g., a 3D stack AND type flash memory) includes a memory cell array, a first global bit line, a second global bit line, and a switch component. The memory cell array is divided into a first memory cell group and a second memory cell group. The first memory cell group has a plurality of first local bit lines and a plurality of first local source lines, and the second memory cell group has a plurality of second local bit lines and a plurality of second local source lines. The switch component is configured to couple the first local source lines to a common source line or couple the second local source lines to the common source line during a plurality of different test modes.

公开(公告)号：US20230337422A1

公开(公告)日：2023-10-19

申请号：US17721222

申请日：2022-04-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng Hao Yeh

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/0483

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a source pillar, a charge storage structure, a first transistor and a second transistor. The gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked. The channel pillar extends through the gate stack structure. The source pillar and the drain pillar are disposed in the channel pillar and electrically connected to the channel pillar. The charge storage structure is located between the plurality of gate layers and the channel pillar. The first transistor is located above the gate stack structure and electrically connected to the drain pillar. The second transistor is located above the gate stack structure and electrically connected to the source pillar.

公开(公告)号：US11678486B2

公开(公告)日：2023-06-13

申请号：US16784167

申请日：2020-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng Hao Yeh ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

公开(公告)号：US11875854B2

公开(公告)日：2024-01-16

申请号：US17710683

申请日：2022-03-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng Hao Yeh ,  Wu-Chin Peng ,  Chih-Ming Lin ,  Hang-Ting Lue

IPC: G11C11/34 ,  G11C8/00 ,  G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line signal generator, a first voltage generator, and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a third voltage and a fourth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.

公开(公告)号：US20230413552A1

公开(公告)日：2023-12-21

申请号：US17845601

申请日：2022-06-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Teng Hao Yeh ,  Cheng-Yu Lee ,  Wei-Chen Chen

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L23/535

Abstract: A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

公开(公告)号：US12156402B2

公开(公告)日：2024-11-26

申请号：US17721222

申请日：2022-04-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng Hao Yeh

IPC: H10B41/27 ,  G11C16/04 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a source pillar, a charge storage structure, a first transistor and a second transistor. The gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked. The channel pillar extends through the gate stack structure. The source pillar and the drain pillar are disposed in the channel pillar and electrically connected to the channel pillar. The charge storage structure is located between the plurality of gate layers and the channel pillar. The first transistor is located above the gate stack structure and electrically connected to the drain pillar. The second transistor is located above the gate stack structure and electrically connected to the source pillar.

公开(公告)号：US20230317167A1

公开(公告)日：2023-10-05

申请号：US17710683

申请日：2022-03-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng Hao Yeh ,  Wu-Chin Peng ,  Chih-Ming Lin ,  Hang-Ting Lue

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line signal generator, a first voltage generator, and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a third voltage and a fourth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.

公开(公告)号：US09748264B1

公开(公告)日：2017-08-29

申请号：US15148485

申请日：2016-05-06

Applicant: Macronix International Co., Ltd.

Inventor： Yu Wei Jiang ,  Teng Hao Yeh

IPC: H01L29/74 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L21/338 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L27/11565 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a substrate, conductive layers, insulating layers, a memory structure including first memory structure clusters and second memory structure clusters, isolation trenches, and common source trenches. The conductive layers and the insulating layers are interlaced and stacked on the substrate. Each first memory structure cluster include first memory structures and each first memory structure cluster include second memory structures. The first and second memory structures penetrate the conductive layers and the insulating layers. Each isolation trench is formed between a first memory structure cluster and a second memory structure cluster. The isolation trenches span horizontally on the substrate in a discontinuous manner separated by gaps. Common source trenches are formed on the substrate that run substantially parallel with the isolation trenches.