公开(公告)号：US20170018500A1

公开(公告)日：2017-01-19

申请号：US14801648

申请日：2015-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug and a liner. The substrate has a conductive region therein. The first dielectric layer, the etch stop layer and the second dielectric layer are sequentially formed on the substrate and have at least one opening therethrough. Besides, the opening has a substantially vertical sidewall. The conductive plug fills in the opening and is electrically connected to the conductive region. The liner surrounds the upper portion of the conductive plug. A method of forming a structure with a conductive plug is further provided.

Abstract translation: 提供了具有导电插塞的结构，其包括基板，第一介电层，蚀刻停止层，第二介电层，导电塞和衬垫。 衬底在其中具有导电区域。 第一电介质层，蚀刻停止层和第二介电层依次形成在基板上并具有至少一个通过其的开口。 此外，开口具有基本垂直的侧壁。 导电插头填充在开口中并且电连接到导电区域。 衬套围绕导电插塞的上部。 还提供了一种用导电插塞形成结构的方法。

公开(公告)号：US09576903B2

公开(公告)日：2017-02-21

申请号：US14801648

申请日：2015-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug and a liner. The substrate has a conductive region therein. The first dielectric layer, the etch stop layer and the second dielectric layer are sequentially formed on the substrate and have at least one opening therethrough. Besides, the opening has a substantially vertical sidewall. The conductive plug fills in the opening and is electrically connected to the conductive region. The liner surrounds the upper portion of the conductive plug. A method of forming a structure with a conductive plug is further provided.

Abstract translation: 提供了具有导电插塞的结构，其包括基板，第一介电层，蚀刻停止层，第二介电层，导电塞和衬垫。 衬底在其中具有导电区域。 第一电介质层，蚀刻停止层和第二介电层依次形成在基板上并具有至少一个通过其的开口。 此外，开口具有基本垂直的侧壁。 导电插头填充在开口中并且电连接到导电区域。 衬套围绕导电插塞的上部。 还提供了一种用导电插塞形成结构的方法。

公开(公告)号：US09337048B2

公开(公告)日：2016-05-10

申请号：US14493608

申请日：2014-09-23

Applicant: Macronix International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

Abstract: A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles.

Abstract translation: 公开了一种在半导体存储器结构中制造字线的方法，其消除了字线之间的桁条，同时保持了阈值电压的稳定分布。 在执行字线蚀刻之前沉积衬垫，然后执行部分字线蚀刻。 衬里的剩余部分被去除，并且字线蚀刻完成以形成具有垂直或锥形轮廓的门。

公开(公告)号：US20160086806A1

公开(公告)日：2016-03-24

申请号：US14493608

申请日：2014-09-23

Applicant: Macronix International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

Abstract: A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles.

Abstract translation: 公开了一种在半导体存储器结构中制造字线的方法，其消除了字线之间的桁条，同时保持了阈值电压的稳定分布。 在执行字线蚀刻之前沉积衬垫，然后执行部分字线蚀刻。 衬里的剩余部分被去除，并且字线蚀刻完成以形成具有垂直或锥形轮廓的门。