公开(公告)号：US20170018500A1

公开(公告)日：2017-01-19

申请号：US14801648

申请日：2015-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug and a liner. The substrate has a conductive region therein. The first dielectric layer, the etch stop layer and the second dielectric layer are sequentially formed on the substrate and have at least one opening therethrough. Besides, the opening has a substantially vertical sidewall. The conductive plug fills in the opening and is electrically connected to the conductive region. The liner surrounds the upper portion of the conductive plug. A method of forming a structure with a conductive plug is further provided.

Abstract translation: 提供了具有导电插塞的结构，其包括基板，第一介电层，蚀刻停止层，第二介电层，导电塞和衬垫。 衬底在其中具有导电区域。 第一电介质层，蚀刻停止层和第二介电层依次形成在基板上并具有至少一个通过其的开口。 此外，开口具有基本垂直的侧壁。 导电插头填充在开口中并且电连接到导电区域。 衬套围绕导电插塞的上部。 还提供了一种用导电插塞形成结构的方法。

公开(公告)号：US09576903B2

公开(公告)日：2017-02-21

申请号：US14801648

申请日：2015-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug and a liner. The substrate has a conductive region therein. The first dielectric layer, the etch stop layer and the second dielectric layer are sequentially formed on the substrate and have at least one opening therethrough. Besides, the opening has a substantially vertical sidewall. The conductive plug fills in the opening and is electrically connected to the conductive region. The liner surrounds the upper portion of the conductive plug. A method of forming a structure with a conductive plug is further provided.

Abstract translation: 提供了具有导电插塞的结构，其包括基板，第一介电层，蚀刻停止层，第二介电层，导电塞和衬垫。 衬底在其中具有导电区域。 第一电介质层，蚀刻停止层和第二介电层依次形成在基板上并具有至少一个通过其的开口。 此外，开口具有基本垂直的侧壁。 导电插头填充在开口中并且电连接到导电区域。 衬套围绕导电插塞的上部。 还提供了一种用导电插塞形成结构的方法。

公开(公告)号：US09337048B2

公开(公告)日：2016-05-10

申请号：US14493608

申请日：2014-09-23

Applicant: Macronix International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

Abstract: A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles.

Abstract translation: 公开了一种在半导体存储器结构中制造字线的方法，其消除了字线之间的桁条，同时保持了阈值电压的稳定分布。 在执行字线蚀刻之前沉积衬垫，然后执行部分字线蚀刻。 衬里的剩余部分被去除，并且字线蚀刻完成以形成具有垂直或锥形轮廓的门。

公开(公告)号：US20160086806A1

公开(公告)日：2016-03-24

申请号：US14493608

申请日：2014-09-23

Applicant: Macronix International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

Abstract: A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles.

Abstract translation: 公开了一种在半导体存储器结构中制造字线的方法，其消除了字线之间的桁条，同时保持了阈值电压的稳定分布。 在执行字线蚀刻之前沉积衬垫，然后执行部分字线蚀刻。 衬里的剩余部分被去除，并且字线蚀刻完成以形成具有垂直或锥形轮廓的门。

公开(公告)号：US08969202B2

公开(公告)日：2015-03-03

申请号：US14174931

申请日：2014-02-07

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC: H01L21/44 ,  H01L21/8234 ,  H01L21/302 ,  H01L21/461 ,  H01L21/283 ,  H01L27/105 ,  H01L21/28 ,  H01L29/49 ,  H01L27/118

CPC classification number: H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

Abstract translation: 以下公开了金属硅化物的制造方法。 提供具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。

公开(公告)号：US08735969B1

公开(公告)日：2014-05-27

申请号：US13670669

申请日：2012-11-07

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Shih-Chang Tsai

IPC: H01L29/66

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L27/101 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure, comprising a plurality of conductive strips and a plurality of insulating strips, is formed on a substrate, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively. The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括堆叠结构，多个第一导电块，多个第一导电层，多个第二导电层和多个导电镶嵌结构。 在衬底上形成包括多个导电条和多个绝缘条的堆叠结构，并且导电条和绝缘条交错。 第一导电块形成在堆叠结构上。 第一导电层和第二导电层分别形成在层叠结构的两个侧壁上。 导电镶嵌结构形成在堆叠结构的两侧，其中每个第一导电块经由第一导电条和每个第二导电条经由每个导电镶嵌结构电连接。

公开(公告)号：US20140154881A1

公开(公告)日：2014-06-05

申请号：US14174931

申请日：2014-02-07

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC: H01L21/283

CPC classification number: H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

Abstract translation: 以下公开了金属硅化物的制造方法。 提供具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。

公开(公告)号：US20140124945A1

公开(公告)日：2014-05-08

申请号：US13670669

申请日：2012-11-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Shih-Chang Tsai

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L27/101 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure, comprising a plurality of conductive strips and a plurality of insulating strips, is formed on a substrate, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively. The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括堆叠结构，多个第一导电块，多个第一导电层，多个第二导电层和多个导电镶嵌结构。 在衬底上形成包括多个导电条和多个绝缘条的堆叠结构，并且导电条和绝缘条交错。 第一导电块形成在堆叠结构上。 第一导电层和第二导电层分别形成在层叠结构的两个侧壁上。 导电镶嵌结构形成在堆叠结构的两侧，其中每个第一导电块经由第一导电条和每个第二导电条经由每个导电镶嵌结构电连接。