公开(公告)号：US20230361026A1

公开(公告)日：2023-11-09

申请号：US17737762

申请日：2022-05-05

申请人： MACRONIX International Co., Ltd.

发明人： Li-Yen Liang

IPC分类号： H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528

CPC分类号： H01L23/5228 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/5283 ,  H01L23/5226

摘要： A semiconductor device may be applicated in a three-dimensional AND flash memory device. The semiconductor device includes a dielectric substrate, a composite stack structure, a vertical pillar array and a resistor. The dielectric substrate includes a first region and a second region. The composite stack structure is located over the dielectric substrate in the first region and the second region. The vertical pillar array is disposed in the composite stack structure in the first region. The resistor is laterally adjacent to the vertical pillar array, extends below the composite stack structure in the second region, extends through the composite stack structure, and extends above the composite stack structure.

公开(公告)号：US11903203B2

公开(公告)日：2024-02-13

申请号：US17461518

申请日：2021-08-30

申请人： MACRONIX International Co., Ltd.

发明人： Min-Feng Hung ,  Li-Yen Liang ,  Chia-Tze Huang

IPC分类号： H01L27/11582 ,  H10B43/27 ,  H10B43/10 ,  G11C16/04

CPC分类号： H10B43/27 ,  H10B43/10 ,  G11C16/0466

摘要： A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure. The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.

公开(公告)号：US20230066310A1

公开(公告)日：2023-03-02

申请号：US17461518

申请日：2021-08-30

申请人： MACRONIX International Co., Ltd.

发明人： Min-Feng Hung ,  Li-Yen Liang ,  Chia-Tze Huang

IPC分类号： H01L27/11582 ,  H01L27/11565

摘要： A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure.
The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.

公开(公告)号：US20240276717A1

公开(公告)日：2024-08-15

申请号：US18168582

申请日：2023-02-14

申请人： MACRONIX International Co., Ltd.

发明人： Li-Yen Liang

IPC分类号： H10B43/27

CPC分类号： H10B43/27

摘要： A memory structure, applicable to a three-dimensional AND flash memory device, is provided. The memory structure includes a substrate, a stack structure, a channel pillar, charge storage structures, a first conductive pillar, a second conductive pillar, and an isolation pillar. The stack structure is located on the substrate and includes first dielectric layers and conductive layers alternately stacked. The channel pillar passes through the stack structure. Each charge storage structure is located between the corresponding conductive layer and the channel pillar. The first conductive pillar and the second conductive pillar are located within the channel pillar. The first conductive pillar and the second conductive pillar are separated from each other. The isolation pillar is located between the first conductive pillar and the second conductive pillar. The top of the isolation pillar is higher than the top of the first conductive pillar and the top of the second conductive pillar.

公开(公告)号：US11844221B2

公开(公告)日：2023-12-12

申请号：US17409431

申请日：2021-08-23

申请人： MACRONIX International Co., Ltd.

发明人： Li-Yen Liang ,  Teng-Hao Yeh

IPC分类号： H10B43/35 ,  H10B43/10 ,  H10B43/40 ,  H01L23/522 ,  H10B43/27

CPC分类号： H10B43/35 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

摘要： A 3D flash memory device such as a 3D AND flash memory device is provided. The 3D flash memory device includes a substrate, a conductive layer, a 3D flash memory array, and through-array vias (TAVs). The substrate includes a memory cell region and a passive device region. The conductive layer is formed on the substrate, and the conductive layer includes: a first circuit disposed at the memory cell region and a second circuit of a passive device disposed at the passive device region. The 3D flash memory array is formed on the first circuit of the memory cell region. The TAVs are respectively formed on the second circuit of the passive device disposed at the passive device region and connected to at least one end of the second circuit.

公开(公告)号：US20230058855A1

公开(公告)日：2023-02-23

申请号：US17409431

申请日：2021-08-23

申请人： MACRONIX International Co., Ltd.

发明人： Li-Yen Liang ,  Teng-Hao Yeh

IPC分类号： H01L27/1157 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11565

摘要： A 3D flash memory device such as a 3D AND flash memory device is provided. The 3D flash memory device includes a substrate, a conductive layer, a 3D flash memory array, and through-array vias (TAVs). The substrate includes a memory cell region and a passive device region. The conductive layer is formed on the substrate, and the conductive layer includes: a first circuit disposed at the memory cell region and a second circuit of a passive device disposed at the passive device region. The 3D flash memory array is formed on the first circuit of the memory cell region. The TAVs are respectively formed on the second circuit of the passive device disposed at the passive device region and connected to at least one end of the second circuit.