公开(公告)号：US20230337426A1

公开(公告)日：2023-10-19

申请号：US17721235

申请日：2022-04-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Chia-Tze Huang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/5283

Abstract: A memory device includes a gate stack structure, a channel pillar, a plurality of conductive pillars, and a charge storage structure. The gate stack structure is located over a dielectric substrate, and includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel pillar extends through the gate stack structure. Each of the conductive pillars includes a body portion and an extension portion. The body portion extends through the gate stack structure and is electrically connected to the channel pillar. The extension portion is below and is electrically isolated from the channel pillar. The charge storage structure is between the channel pillar and the plurality of gate layers.

公开(公告)号：US20230066310A1

公开(公告)日：2023-03-02

申请号：US17461518

申请日：2021-08-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Min-Feng Hung ,  Li-Yen Liang ,  Chia-Tze Huang

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure.
The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.

公开(公告)号：US12268000B2

公开(公告)日：2025-04-01

申请号：US17721235

申请日：2022-04-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Chia-Tze Huang

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes a gate stack structure, a channel pillar, a plurality of conductive pillars, and a charge storage structure. The gate stack structure is located over a dielectric substrate, and includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel pillar extends through the gate stack structure. Each of the conductive pillars includes a body portion and an extension portion. The body portion extends through the gate stack structure and is electrically connected to the channel pillar. The extension portion is below and is electrically isolated from the channel pillar. The charge storage structure is between the channel pillar and the plurality of gate layers.

公开(公告)号：US20240357811A1

公开(公告)日：2024-10-24

申请号：US18302806

申请日：2023-04-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Chia-Tze Huang

IPC: H10B43/27 ,  H01L23/60

CPC classification number: H10B43/27 ,  H01L23/60

Abstract: A memory device can be applied to a 3D AND flash memory. The memory device includes a substrate, a first stacked structure, a second stacked structure, a channel structure, an insulating pillar, a through via and a conductive layer. The substrate has a memory array region and a staircase region. The first stacked structure is disposed on the substrate in the memory array region and includes first dielectric layers and gates alternately stacked. The second stacked structure is disposed on the substrate in the staircase region and includes second dielectric layers and stairs alternately stacked. The channel structure penetrates through the first stacked structure in the memory array region. The insulating pillar penetrates through the second stacked structure in the staircase region. The through via penetrates through the insulating pillar in the staircase region. The conductive layer surrounds the sidewall of the insulating pillar.

公开(公告)号：US11903203B2

公开(公告)日：2024-02-13

申请号：US17461518

申请日：2021-08-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Min-Feng Hung ,  Li-Yen Liang ,  Chia-Tze Huang

IPC: H01L27/11582 ,  H10B43/27 ,  H10B43/10 ,  G11C16/04

CPC classification number: H10B43/27 ,  H10B43/10 ,  G11C16/0466

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure. The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.

公开(公告)号：US12120873B2

公开(公告)日：2024-10-15

申请号：US17483505

申请日：2021-09-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Chia-Tze Huang

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Provided is a three-dimensional flash memory including a substrate, a stack structure, a stop layer, two slit trenches, a plurality of vertical channel structures, and a plurality of slit holes. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The stop layer is disposed between the substrate and the stack structure. The two slit trenches penetrate through the stack structure to expose the stop layer. The vertical channel structures are disposed between the two slit trenches and penetrate through the stack structure and the stop layer. The slit holes are discretely disposed between the vertical channel structures, and penetrate through the stack structure to expose the stop layer. A method of forming the three-dimensional flash memory is also provided.

公开(公告)号：US20240315020A1

公开(公告)日：2024-09-19

申请号：US18182385

申请日：2023-03-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Chia-Tze Huang

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A semiconductor structure including a substrate, a stacked structure, a support pillar, and a channel pillar is provided. The substrate includes a peripheral region and an array region. The stacked structure is located on the substrate. The support pillar is located in the peripheral region. The support pillar passes through the stacked structure. The channel pillar is located in the array region. The channel pillar passes through the stacked structure. A thickness of the support pillar is greater than a thickness of the channel pillar.

公开(公告)号：US20230085996A1

公开(公告)日：2023-03-23

申请号：US17483505

申请日：2021-09-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Chia-Tze Huang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: Provided is a three-dimensional flash memory including a substrate, a stack structure, a stop layer, two slit trenches, a plurality of vertical channel structures, and a plurality of slit holes. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The stop layer is disposed between the substrate and the stack structure. The two slit trenches penetrate through the stack structure to expose the stop layer. The vertical channel structures are disposed between the two slit trenches and penetrate through the stack structure and the stop layer. The slit holes are discretely disposed between the vertical channel structures, and penetrate through the stack structure to expose the stop layer. A method of forming the three-dimensional flash memory is also provided.