公开(公告)号：US20220399361A1

公开(公告)日：2022-12-15

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US08933566B2

公开(公告)日：2015-01-13

申请号：US14301039

申请日：2014-06-10

Applicant: Macronix International Co., Ltd.

Inventor： Lo Yueh Lin

IPC: H01L21/44 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/42356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.

Abstract translation: 在半导体中的多层线中的多晶硅和氧化物层的基本上同时等离子体蚀刻允许多层线路的增强的临界尺寸和纵横比。 增加多层线宽比可能是可能的，从而在半导体技术中允许提高效率，更大的存储容量和更小的关键尺寸。

公开(公告)号：US12048154B2

公开(公告)日：2024-07-23

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US20140299973A1

公开(公告)日：2014-10-09

申请号：US14301039

申请日：2014-06-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lo Yueh Lin

IPC: H01L29/423 ,  H01L27/115

CPC classification number: H01L29/42356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.

Abstract translation: 在半导体中的多层线中的多晶硅和氧化物层的基本上同时等离子体蚀刻允许多层线路的增强的临界尺寸和纵横比。 增加多层线宽比可能是可能的，从而在半导体技术中允许提高效率，更大的存储容量和更小的关键尺寸。

公开(公告)号：US08778796B2

公开(公告)日：2014-07-15

申请号：US13648792

申请日：2012-10-10

Applicant: Macronix International Co., LTD

Inventor： Lo Yueh Lin

IPC: H01L21/44

CPC classification number: H01L29/42356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.