公开(公告)号：US09950924B2

公开(公告)日：2018-04-24

申请号：US14985388

申请日：2015-12-30

申请人： mCube, Inc.

发明人： Sudheer S. Sridharamurthy ,  Te-Hse Terrence Lee ,  Ali J. Rastegar ,  Mugurel Stancu ,  Xiao Charles Yang

IPC分类号： B81C1/00 ,  B81B7/00 ,  H01L27/06 ,  B81B3/00

CPC分类号： B81C1/00801 ,  B81B3/0013 ,  B81B3/0086 ,  B81B7/0022 ,  B81B7/0064 ,  B81B2203/0163 ,  B81B2207/094 ,  B81C1/00238 ,  B81C2201/0132 ,  B81C2201/05 ,  B81C2203/0735 ,  H01L27/0688

摘要： A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

公开(公告)号：US20130236988A1

公开(公告)日：2013-09-12

申请号：US13788503

申请日：2013-03-07

申请人： MCUBE, INC.

发明人： Sudheer S. Sridharamurthy ,  Te-Hse Terrence Lee ,  Ali J. Rastegar ,  Mugurel Stancu ,  Xiao Charles Yang

IPC分类号： H01L29/66

CPC分类号： B81C1/00801 ,  B81B3/0013 ,  B81B3/0086 ,  B81B7/0022 ,  B81B7/0064 ,  B81B2203/0163 ,  B81B2207/094 ,  B81C1/00238 ,  B81C2201/0132 ,  B81C2201/05 ,  B81C2203/0735 ,  H01L27/0688

摘要： A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

摘要翻译： 一种用于制造集成的MEMS-CMOS器件的方法使用微型制造工艺，其通过在CMOS的顶部上结合机械结构晶片并使用等离子体蚀刻来蚀刻机械层来实现在常规CMOS结构之上的移动机械结构（MEMS） 工艺，如深层反应离子蚀刻（DRIE）。 在蚀刻机械层期间，直接连接到机械层的CMOS器件暴露于等离子体。 这有时会导致对CMOS电路的永久性损坏，称为等离子体诱发损伤（PID）。 本发明的实施例提出了防止或减少该PID并且通过接地并为CMOS电路提供替代路径来保护下面的CMOS电路直到MEMS层被完全蚀刻的方法和结构。

公开(公告)号：US20160176708A1

公开(公告)日：2016-06-23

申请号：US14985388

申请日：2015-12-30

申请人： mCube, Inc.

发明人： Sudheer S. Sridharamurthy ,  Te-Hse Terrence Lee ,  Ali J. Rastegar ,  Mugurel Stancu ,  Xiao Charles Yang

IPC分类号： B81C1/00 ,  B81B7/00

CPC分类号： B81C1/00801 ,  B81B3/0013 ,  B81B3/0086 ,  B81B7/0022 ,  B81B7/0064 ,  B81B2203/0163 ,  B81B2207/094 ,  B81C1/00238 ,  B81C2201/0132 ,  B81C2201/05 ,  B81C2203/0735 ,  H01L27/0688

摘要： A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

摘要翻译： 一种用于制造集成的MEMS-CMOS器件的方法使用微型制造工艺，其通过在CMOS的顶部上结合机械结构晶片并使用等离子体蚀刻来蚀刻机械层来实现在常规CMOS结构之上的移动机械结构（MEMS） 工艺，如深层反应离子蚀刻（DRIE）。 在蚀刻机械层期间，直接连接到机械层的CMOS器件暴露于等离子体。 这有时会导致对CMOS电路的永久性损坏，称为等离子体诱发损伤（PID）。 本发明的实施例提出了防止或减少该PID并且通过接地并为CMOS电路提供替代路径来保护下面的CMOS电路直到MEMS层被完全蚀刻的方法和结构。

公开(公告)号：US20160060102A1

公开(公告)日：2016-03-03

申请号：US13855988

申请日：2013-04-03

申请人： MCube, Inc.

发明人： Xiao Charles Yang

IPC分类号： B81B7/00 ,  H01L27/092

CPC分类号： B81B7/008 ,  B81B7/0038 ,  B81B2207/094 ,  B81C1/00238 ,  B81C1/00246 ,  H01L21/8221 ,  H01L27/092 ,  H01L29/0649 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A monolithically integrated CMOS and MEMS device. The device includes a first semiconductor substrate having a first surface region and one or more CMOS IC devices on a CMOS IC device region overlying the first surface region. The CMOS IC device region can also have a CMOS surface region. A bonding material can be provided overlying the CMOS surface region to form an interface by which a second semiconductor substrate can be joined to the CMOS surface region. The second semiconductor substrate has a second surface region coupled to the CMOS surface region by bonding the second surface region to the bonding material. The second semiconductor substrate includes one or more first air dielectric regions. One or more free standing MEMS structures can be formed within one or more portions of the processed first substrate.

摘要翻译： 单片集成CMOS和MEMS器件。 该器件包括第一半导体衬底，该第一半导体衬底具有覆盖第一表面区域的CMOS IC器件区域上的第一表面区域和一个或多个CMOS IC器件。 CMOS IC器件区域也可以具有CMOS表面区域。 可以提供覆盖CMOS表面区域的接合材料，以形成可将第二半导体衬底接合到CMOS表面区域的界面。 第二半导体衬底具有通过将第二表面区域结合到接合材料而耦合到CMOS表面区域的第二表面区域。 第二半导体衬底包括一个或多个第一空气介电区域。 可以在经处理的第一基板的一个或多个部分内形成一个或多个独立的MEMS结构。

公开(公告)号：US09276080B2

公开(公告)日：2016-03-01

申请号：US13788503

申请日：2013-03-07

申请人： MCube, Inc.

发明人： Sudheer S. Sridharamurthy ,  Te-Hse Terrence Lee ,  Ali J. Rastegar ,  Mugurel Stancu ,  Xiao Charles Yang

IPC分类号： H01L29/66 ,  H01L27/06 ,  B81B3/00 ,  B81C1/00

CPC分类号： B81C1/00801 ,  B81B3/0013 ,  B81B3/0086 ,  B81B7/0022 ,  B81B7/0064 ,  B81B2203/0163 ,  B81B2207/094 ,  B81C1/00238 ,  B81C2201/0132 ,  B81C2201/05 ,  B81C2203/0735 ,  H01L27/0688

摘要： A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

摘要翻译： 一种用于制造集成的MEMS-CMOS器件的方法使用微型制造工艺，其通过在CMOS的顶部上结合机械结构晶片并使用等离子体蚀刻来蚀刻机械层来实现在常规CMOS结构之上的移动机械结构（MEMS） 工艺，如深层反应离子蚀刻（DRIE）。 在蚀刻机械层期间，直接连接到机械层的CMOS器件暴露于等离子体。 这有时会导致对CMOS电路的永久性损坏，称为等离子体诱发损伤（PID）。 本发明的实施例提出了防止或减少该PID并且通过接地并为CMOS电路提供替代路径来保护下面的CMOS电路直到MEMS层被完全蚀刻的方法和结构。