公开(公告)号：US20240230720A1

公开(公告)日：2024-07-11

申请号：US18150587

申请日：2023-01-05

Applicant: MEDIATEK INC.

Inventor： Long-Kun YU ,  Zi-Ren LIU ,  Ching-Wen CHENG ,  Hsun-Wei PAO ,  Wai-Ling CHENG ,  Ping CHEN ,  Jie-Fan LAI ,  Yeng-Ming TZENG ,  Hung-Chuan CHEN ,  Chia-Hua CHOU ,  Bing-Shiun WANG ,  Chia-Lung CHUANG ,  Duen-Yi HO ,  Che-Chi HUANG

IPC: G01R15/14

CPC classification number: G01R15/144

Abstract: A detection device includes a substrate and a die. The substrate provides a first voltage. The die is disposed adjacent to the substrate. The die includes a plurality of resistor paths, a selection circuit, an ADC (Analog-to-Digital Converter), and a digital circuit. The selection circuit selects one of the resistor paths as a target path. The target path provides a second voltage. The ADC generates a digital signal according to the first voltage and the second voltage. The digital circuit processes the digital signal.

公开(公告)号：US20140043925A1

公开(公告)日：2014-02-13

申请号：US14054249

申请日：2013-10-15

Applicant: MediaTek Inc.

Inventor： Chih-Hsin LIN ,  Tsung-Huang CHEN ,  Bing-Shiun WANG ,  Jen-Pin SU

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1093

Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data.

Abstract translation: 提供双倍数据速率伪SRAM（DDR PSRAM）。 DDR PSRAM包括数据接收器，存储器和地址解码器。 数据接收器根据时钟通过公共总线从控制器接收第一单个数据速率数据。 地址解码器解码第一单个数据速率数据以获得存储器的地址。 数据接收器将双倍数据速率数据存储到存储器的地址中。 DDR PSRAM还包括数据发送器和数据选通产生单元。 数据发送器获取存储在存储器地址中的数据，并根据获得的数据向控制器提供双数据速率数据，数据选通产生单元将数据选通信号提供给控制器，并响应于 双倍数据速率数据。