公开(公告)号：US20140189415A1

公开(公告)日：2014-07-03

申请号：US14139951

申请日：2013-12-24

Applicant: MediaTek Inc.

Inventor： Tsung-Huang CHEN ,  Li-Chun TU ,  Wen-Chi CHAO

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F13/423

Abstract: A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.

Abstract translation: 用于处理器和外围设备之间的通信的媒体外围接口包括时钟端口，多个数据I / O和数据选通端口。 时钟端口用于将时钟信号传送到外围设备。 数据I / O被提供用于命令传送到外围设备，以及用于数据传送到外围设备。 数据选通端口用于根据处理器向外围设备发出的指令将数据选通信号传送到外围设备或从外围设备传送数据选通信号。 根据时钟信号，捕获通过数据I / O传送的命令信息。 根据数据选通信号的上升沿和下降沿，捕获通过数据I / O传输的数据。

公开(公告)号：US20140043925A1

公开(公告)日：2014-02-13

申请号：US14054249

申请日：2013-10-15

Applicant: MediaTek Inc.

Inventor： Chih-Hsin LIN ,  Tsung-Huang CHEN ,  Bing-Shiun WANG ,  Jen-Pin SU

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1093

Abstract: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory. The DDR PSRAM also includes a data transmitter and a data strobe generating unit. The data transmitter obtains data stored in the address of the memory and provides a double data rate data to the controller according to the obtained data, and the data strobe generating unit a data strobe signal to the controller and toggling the data strobe signal in response to the double data rate data.

Abstract translation: 提供双倍数据速率伪SRAM（DDR PSRAM）。 DDR PSRAM包括数据接收器，存储器和地址解码器。 数据接收器根据时钟通过公共总线从控制器接收第一单个数据速率数据。 地址解码器解码第一单个数据速率数据以获得存储器的地址。 数据接收器将双倍数据速率数据存储到存储器的地址中。 DDR PSRAM还包括数据发送器和数据选通产生单元。 数据发送器获取存储在存储器地址中的数据，并根据获得的数据向控制器提供双数据速率数据，数据选通产生单元将数据选通信号提供给控制器，并响应于 双倍数据速率数据。