公开(公告)号：US20240230720A1

公开(公告)日：2024-07-11

申请号：US18150587

申请日：2023-01-05

Applicant: MEDIATEK INC.

Inventor： Long-Kun YU ,  Zi-Ren LIU ,  Ching-Wen CHENG ,  Hsun-Wei PAO ,  Wai-Ling CHENG ,  Ping CHEN ,  Jie-Fan LAI ,  Yeng-Ming TZENG ,  Hung-Chuan CHEN ,  Chia-Hua CHOU ,  Bing-Shiun WANG ,  Chia-Lung CHUANG ,  Duen-Yi HO ,  Che-Chi HUANG

IPC: G01R15/14

CPC classification number: G01R15/144

Abstract: A detection device includes a substrate and a die. The substrate provides a first voltage. The die is disposed adjacent to the substrate. The die includes a plurality of resistor paths, a selection circuit, an ADC (Analog-to-Digital Converter), and a digital circuit. The selection circuit selects one of the resistor paths as a target path. The target path provides a second voltage. The ADC generates a digital signal according to the first voltage and the second voltage. The digital circuit processes the digital signal.

公开(公告)号：US20240312893A1

公开(公告)日：2024-09-19

申请号：US18594446

申请日：2024-03-04

Applicant: MEDIATEK INC.

Inventor： Hui-Chi TANG ,  Shih-Yi SYU ,  Hao-Ju WANG ,  Pei-San CHEN ,  Duen-Yi HO

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/14361

Abstract: An electronic device is provided. The electronic device includes a base and a semiconductor device. The base has a top surface and a bottom surface. The semiconductor device is disposed on the top surface of the base. The semiconductor device has a device edge located within the base in a top view. The base has a unit pad array which is covered by the semiconductor device and electrically connected to the semiconductor device. The unit pad array includes a first pad region composed of a first row and a second row of the unit pad array. The first pad region includes first pads for transmitting commands and addresses to and from the semiconductor device. The first row of the unit pad array is arranged so that it is closer to the device edge than the second row of the unit pad array.

公开(公告)号：US20220367430A1

公开(公告)日：2022-11-17

申请号：US17739295

申请日：2022-05-09

Applicant: MEDIATEK INC.

Inventor： Yi-Jyun LEE ,  Duen-Yi HO ,  Hsing-Chih LIU ,  Che-Hung KUO

IPC: H01L25/16 ,  H01L49/02 ,  H01L23/498

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

公开(公告)号：US20190098747A1

公开(公告)日：2019-03-28

申请号：US16114669

申请日：2018-08-28

Applicant: MEDIATEK INC.

Inventor： Duen-Yi HO ,  Hung-Chuan CHEN ,  Shang-Pin CHEN

IPC: H05K1/02 ,  H01L23/00 ,  G06F13/40 ,  H01L23/498

Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

公开(公告)号：US20240371781A1

公开(公告)日：2024-11-07

申请号：US18654239

申请日：2024-05-03

Applicant: MEDIATEK INC.

Inventor： Shu-Yuan TSENG ,  Sheng-Yuan FU ,  Duen-Yi HO ,  Chia-Yu JIN

IPC: H01L23/538 ,  H01L25/065

Abstract: An electronic device used in the Universal Chiplet Interconnect Express (UCIe) standard is provided. The electronic device includes a substrate and first and second semiconductor devices. The first and second semiconductor devices are disposed on a top surface of the substrate. The substrate includes an interconnect structure electrically connected between the first and second semiconductor devices. The interconnect structure includes a first pad, a first signal trace and first and second via structures. The first pad is located on the top surface of the substrate. The first signal trace is covered by the first and second semiconductor devices. The first via structure is electrically connected between the first pad and the first signal trace. The second via structure is electrically connected between the first via structure and the first signal trace. The first via structure is misaligned with the second via structure.

公开(公告)号：US20230046413A1

公开(公告)日：2023-02-16

申请号：US17812786

申请日：2022-07-15

Applicant: MEDIATEK INC.

Inventor： Tai-Yu CHEN ,  Chin-Lai CHEN ,  Hsiao-Yun CHEN ,  Wen-Sung HSU ,  Haw-Kuen SU ,  Duen-Yi HO ,  Bo-Jiun YANG ,  Ta-Jen YU ,  Bo-Hao MA

IPC: H01L25/10 ,  H01L25/18

Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.

公开(公告)号：US20170263570A1

公开(公告)日：2017-09-14

申请号：US15411077

申请日：2017-01-20

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou LIN ,  Duen-Yi HO

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.