-
公开(公告)号：US09746866B2
公开(公告)日：2017-08-29
申请号：US14599553
申请日：2015-01-19
Applicant: MEDIATEK INC.
Inventor： Che-Yuan Jao , Chen-Feng Chiang
CPC classification number: G05F3/02 , G06F1/26 , G06F1/3296 , Y02D10/172
Abstract: One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.
-
公开(公告)号：US20150338870A1
公开(公告)日：2015-11-26
申请号：US14599553
申请日：2015-01-19
Applicant: MEDIATEK INC.
Inventor： Che-Yuan Jao , Chen-Feng Chiang
IPC: G05F3/02
CPC classification number: G05F3/02 , G06F1/26 , G06F1/3296 , Y02D10/172
Abstract: One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.
Abstract translation: 本申请的一个实施例公开了一种包括驱动电路的控制电路，该驱动电路包括电压调节电路，第一晶体管和第二晶体管。 第一晶体管包括：第一端子; 第二个终端 以及控制端子，用于接收从至少控制电路的工作电压产生的偏置电压。 第二晶体管包括：第一端子，耦合到第一晶体管的第二端子; 第二端子，用于接收第一预定电压; 以及用于接收控制电压的控制端子。 还公开了一种包括控制电路的控制系统。
-
Patent Agency Ranking
公开(公告)号：US20170315577A1
公开(公告)日：2017-11-02
申请号：US15654694
申请日：2017-07-19
Applicant: MEDIATEK INC.
Inventor： Che-Yuan Jao , Chen-Feng Chiang
CPC classification number: G05F3/02 , G06F1/26 , G06F1/3296 , Y02D10/172
Abstract: A control circuit comprising a driving circuit, which comprises a voltage adjusting circuit for generating a control voltage, and comprises a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. The control circuit further comprises: a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a voltage selecting circuit, for outputting one of the candidate voltage output from the candidate voltage selecting circuit and a ground voltage as the bias voltage.
-
公开(公告)号：US09798345B1
公开(公告)日：2017-10-24
申请号：US15654694
申请日：2017-07-19
Applicant: MEDIATEK INC.
Inventor： Che-Yuan Jao , Chen-Feng Chiang
CPC classification number: G05F3/02 , G06F1/26 , G06F1/3296 , Y02D10/172
Abstract: A control circuit comprising a driving circuit, which comprises a voltage adjusting circuit for generating a control voltage, and comprises a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. The control circuit further comprises: a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a voltage selecting circuit, for outputting one of the candidate voltage output from the candidate voltage selecting circuit and a ground voltage as the bias voltage.
-
公开(公告)号：US20170093152A1
公开(公告)日：2017-03-30
申请号：US15271268
申请日：2016-09-21
Applicant: MEDIATEK Inc.
Inventor： Che-Yuan Jao , Bo-Shih Huang
IPC: H02H9/04
CPC classification number: H02H9/046 , H01L23/60 , H01L27/0248 , H01L2924/14
Abstract: An ESD protected IC includes: at least one functional circuitry, coupled to a first voltage supply and a second voltage supply, the functional circuitry including at least one functional package ball; and at least one ESD detection circuit, coupled to the second voltage supply, the ESD detection circuit free of being coupled to the first voltage supply, and further free of being coupled to the functional package ball of the functional circuitry.
-
公开(公告)号：US20230138324A1
公开(公告)日：2023-05-04
申请号：US17902912
申请日：2022-09-05
Applicant: MEDIATEK INC.
Inventor： Yu-Cheng Liao , Bo-Shih Huang , Che-Yuan Jao , Yi-Chieh Lin
IPC: H01L23/60 , H01L23/498 , H01L23/31 , H01L23/00
Abstract: The present invention provides a package including a first pad, a die and at least one package ESD component is disclosed. The first pad is configured to receive a signal from a device external to the package. The die comprises a second pad and an internal circuit, wherein the internal circuit is configured to receive the signal from the first pad via the second pad. The at least one ESD component is positioned outside the die.
-
公开(公告)号：US09344086B2
公开(公告)日：2016-05-17
申请号：US14173285
申请日：2014-02-05
Applicant: MediaTek Inc.
Inventor： Che-Yuan Jao
CPC classification number: H03K19/00 , H03K5/08 , H03K5/2472
Abstract: A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.
Abstract translation: 提供了一种用于核心电路的接收电路，并且包括第一接收路径单元。 第一接收路径单元能够接收输入信号，并根据输入信号向核心电路输出输出信号。 第一接收路径单元包括能够在核心电路的核心电源域中操作并接收第一钳位信号的输入缓冲器。 当输入信号的电平基本上等于或低于第一预定电压电平时，输入信号被传递到输入缓冲器以用作第一钳位信号，并且输入缓冲器能够输出输出信号 核心电源域根据第一个钳位信号。 当输入信号的电平高于第一预定电压电平时，输入信号不会传递到输入缓冲器。
-
-
-
-
-
-
Search Results
7
records
(took 0.011 seconds)
