公开(公告)号：US10027321B2

公开(公告)日：2018-07-17

申请号：US14746856

申请日：2015-06-23

Applicant: MEDIATEK INC.

Inventor： Chen-Feng Chiang ,  An-Siou Li

IPC: H03K17/0814 ,  H03K17/687 ,  H03K19/0185 ,  H03K17/693 ,  H03K19/00 ,  H03K19/003

Abstract: An I/O driving circuit comprising a post driver. The post driver comprises: a first switch device, comprising a first terminal coupled to an I/O voltage, and comprising a second terminal, wherein the first switch device provides an initial driving voltage at the second terminal of the first switch device; and a first voltage providing device, comprising a first terminal coupled to the second terminal of the first switch device, and comprising a second terminal. The first voltage providing device is configured to provide a driving voltage at the second terminal of the first voltage providing device via providing a voltage drop to the initial driving voltage.

公开(公告)号：US09256245B2

公开(公告)日：2016-02-09

申请号：US14602562

申请日：2015-01-22

Applicant: MediaTek Inc.

Inventor： Chen-Feng Chiang ,  Kai-Hsin Chen ,  Ming-Shi Liou ,  Chih-Tsung Yao

IPC: G11C7/00 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G06F1/10 ,  G06F13/16 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4094

Abstract: A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.

Abstract translation: 时钟树电路包括时钟源和树电路。 时钟源产生一个信号。 树电路至少包括五个驱动单元和金属连接元件。 第一驱动单元具有用于接收信号的输入端子和耦合到第一节点的输出端子。 第二驱动单元具有耦合到第一节点的输入端子和耦合到第二节点的输出端子。 第三驱动单元具有耦合到第一节点的输入端子和耦合到第三节点的输出端子。 第四驱动单元具有耦合到第二节点的输入端子。 第五驱动单元具有耦合到第三节点的输入端。 金属连接元件耦合在第二节点和第三节点之间，并被配置为短路元件。

公开(公告)号：US09746866B2

公开(公告)日：2017-08-29

申请号：US14599553

申请日：2015-01-19

Applicant: MEDIATEK INC.

Inventor： Che-Yuan Jao ,  Chen-Feng Chiang

IPC: H03K3/00 ,  G05F3/02 ,  G06F1/32 ,  G06F1/26

CPC classification number: G05F3/02 ,  G06F1/26 ,  G06F1/3296 ,  Y02D10/172

Abstract: One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.

公开(公告)号：US09557764B2

公开(公告)日：2017-01-31

申请号：US14980362

申请日：2015-12-28

Applicant: MediaTek Inc.

Inventor： Chen-Feng Chiang ,  Kai-Hsin Chen ,  Ming-Shi Liou ,  Chih-Tsung Yao

IPC: G11C7/00 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/4094 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10

CPC classification number: G06F1/10 ,  G06F13/16 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4094

Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.

Abstract translation: 时钟树电路包括第一时钟源，产生第一信号和第一树电路。 第一时钟树电路包括用于接收第一信号的第一驱动级，连接到第一驱动级的第二驱动级，连接到第二驱动级的第三驱动级和耦合在不同节点之间的金属连接元件 并配置为短路元件。

公开(公告)号：US20170315577A1

公开(公告)日：2017-11-02

申请号：US15654694

申请日：2017-07-19

Applicant: MEDIATEK INC.

Inventor： Che-Yuan Jao ,  Chen-Feng Chiang

IPC: G05F3/02 ,  G06F1/26 ,  G06F1/32

CPC classification number: G05F3/02 ,  G06F1/26 ,  G06F1/3296 ,  Y02D10/172

Abstract: A control circuit comprising a driving circuit, which comprises a voltage adjusting circuit for generating a control voltage, and comprises a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. The control circuit further comprises: a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a voltage selecting circuit, for outputting one of the candidate voltage output from the candidate voltage selecting circuit and a ground voltage as the bias voltage.

公开(公告)号：US09798345B1

公开(公告)日：2017-10-24

申请号：US15654694

申请日：2017-07-19

Applicant: MEDIATEK INC.

Inventor： Che-Yuan Jao ,  Chen-Feng Chiang

IPC: H03K3/00 ,  G05F3/02 ,  G06F1/32 ,  G06F1/26

CPC classification number: G05F3/02 ,  G06F1/26 ,  G06F1/3296 ,  Y02D10/172

Abstract: A control circuit comprising a driving circuit, which comprises a voltage adjusting circuit for generating a control voltage, and comprises a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. The control circuit further comprises: a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a voltage selecting circuit, for outputting one of the candidate voltage output from the candidate voltage selecting circuit and a ground voltage as the bias voltage.

公开(公告)号：US20220138570A1

公开(公告)日：2022-05-05

申请号：US17495489

申请日：2021-10-06

Applicant: MediaTek Inc.

Inventor： Chia-Yu Tsai ,  Hung-Hao Shen ,  Chen-Feng Chiang ,  Chung-An Wang ,  Yiju Ting ,  Chia-Shun Yeh ,  Chin-Tang Lai ,  Feng-Ming Tsai ,  Kai-En Yang

IPC: G06N3/08

Abstract: A system performs the operations of a neural network agent and a circuit simulator for analog circuit sizing. The system receives an input indicating a specification of an analog circuit and design parameters. The system iteratively searches a design space until a circuit size is found to satisfy the specification and the design parameters. In each iteration, the neural network agent calculates measurement estimates for random sample generated in a trust region, which is a portion of the design space. Based on the measurement estimate, the system identifies a candidate size that optimizes a value metric. The circuit simulator receives the candidate size and generates a simulation measurement. The system calculates updates to weights of the neural network agent and the trust region for a next iteration based on, at least in part, the simulation measurement.

公开(公告)号：US20160173085A1

公开(公告)日：2016-06-16

申请号：US14746856

申请日：2015-06-23

Applicant: Mediatek Inc.

Inventor： Chen-Feng Chiang ,  An-Siou Li

IPC: H03K17/687 ,  H03K17/693

CPC classification number: H03K17/6871 ,  H03K17/08142 ,  H03K17/693 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018521

Abstract: An I/O driving circuit comprising a post driver. The post driver comprises: a first switch device, comprising a first terminal coupled to an I/O voltage, and comprising a second terminal, wherein the first switch device provides an initial driving voltage at the second terminal of the first switch device; and a first voltage providing device, comprising a first terminal coupled to the second terminal of the first switch device, and comprising a second terminal. The first voltage providing device is configured to provide a driving voltage at the second terminal of the first voltage providing device via providing a voltage drop to the initial driving voltage.

Abstract translation: 一种包括后置驱动器的I / O驱动电路。 所述后驱动器包括：第一开关装置，包括耦合到I / O电压的第一端子，并且包括第二端子，其中所述第一开关装置在所述第一开关装置的所述第二端子处提供初始驱动电压; 以及第一电压提供装置，包括耦合到第一开关装置的第二端子的第一端子，并且包括第二端子。 第一电压提供装置被配置为通过向初始驱动电压提供电压降来在第一电压提供装置的第二端提供驱动电压。

公开(公告)号：US20150338870A1

公开(公告)日：2015-11-26

申请号：US14599553

申请日：2015-01-19

Applicant: MEDIATEK INC.

Inventor： Che-Yuan Jao ,  Chen-Feng Chiang

IPC: G05F3/02

CPC classification number: G05F3/02 ,  G06F1/26 ,  G06F1/3296 ,  Y02D10/172

Abstract: One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.

Abstract translation: 本申请的一个实施例公开了一种包括驱动电路的控制电路，该驱动电路包括电压调节电路，第一晶体管和第二晶体管。 第一晶体管包括：第一端子; 第二个终端 以及控制端子，用于接收从至少控制电路的工作电压产生的偏置电压。 第二晶体管包括：第一端子，耦合到第一晶体管的第二端子; 第二端子，用于接收第一预定电压; 以及用于接收控制电压的控制端子。 还公开了一种包括控制电路的控制系统。