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1.发明授权公开(公告)号：US10176853B2
公开(公告)日：2019-01-08
申请号：US15499876
申请日：2017-04-27
Applicant: MEDIATEK INC.
Inventor： Chi-Hao Hong , Dao-Ping Wang , Yi-Wei Chen , Yi-Ping Kuo , Shu-Lin Lai
Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.
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Patent Agency Ranking
公开(公告)号：US20240312557A1
公开(公告)日：2024-09-19
申请号：US18443347
申请日：2024-02-16
Applicant: MEDIATEK INC.
Inventor： Che-Wei Chou , Ya-Ting Yang , Shu-Lin Lai , Chi-Kai Hsieh , Yi-Ping Kuo , Chi-Hao Hong , Jia-Jing Chen , Yi-Te Chiu , Jiann-Tseng Huang
CPC classification number: G11C29/702 , G11C29/56008 , G11C29/56016
Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.
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3.发明公开公开(公告)号：US20240233786A9
公开(公告)日：2024-07-11
申请号：US18371441
申请日：2023-09-21
Applicant: MEDIATEK INC.
Inventor： Chi-Hao Hong
CPC classification number: G11C7/1069 , G11C7/106 , G11C7/12
Abstract: A memory includes a memory array and a single-ended sense amplifier circuit. The memory array includes wordlines, bitlines, and memory cells. The bitlines include a first bitline, routed on a first metal layer but not a second metal layer, and a second bitline, routed on the first metal layer and the second metal layer. Each of the memory cells is coupled to one of the wordlines. The memory cells include a first group of memory cells, coupled to the first bitline, and a second group of memory cells, coupled to the second bitline, where the first group of memory cells and the second group of memory cells are located at a same column. The single-ended sense amplifier circuit performs a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled.
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4.发明公开公开(公告)号：US20240135976A1
公开(公告)日：2024-04-25
申请号：US18371441
申请日：2023-09-20
Applicant: MEDIATEK INC.
Inventor： Chi-Hao Hong
CPC classification number: G11C7/1069 , G11C7/106 , G11C7/12
Abstract: A memory includes a memory array and a single-ended sense amplifier circuit. The memory array includes wordlines, bitlines, and memory cells. The bitlines include a first bitline, routed on a first metal layer but not a second metal layer, and a second bitline, routed on the first metal layer and the second metal layer. Each of the memory cells is coupled to one of the wordlines. The memory cells include a first group of memory cells, coupled to the first bitline, and a second group of memory cells, coupled to the second bitline, where the first group of memory cells and the second group of memory cells are located at a same column. The single-ended sense amplifier circuit performs a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled.
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公开(公告)号：US20240105259A1
公开(公告)日：2024-03-28
申请号：US18228621
申请日：2023-07-31
Applicant: MEDIATEK INC.
Inventor： Weinan Liao , Chi-Hao Hong
IPC: G11C11/418 , G11C11/419
CPC classification number: G11C11/418 , G11C11/419
Abstract: A pseudo multi-port memory includes a memory array, a row decoder circuit, a timing controller circuit, a sense amplifier circuit, and a write driver circuit. The timing controller circuit outputs a timing control signal to the row decoder circuit, wherein during one memory clock cycle, the row decoder circuit is controlled by the timing control signal to make a read wordline (RWL) signal have an enable pulse and a write wordline (WWL) signal have multiple enable pulses. During one memory clock cycle, the sense amplifier circuit performs read operations upon a selected memory cell when the selected RWL is enabled by the enable pulse and the selected WWL is enabled by at least one first enable pulse, and the write driver circuit performs a write operation upon the selected memory cell when the selected WWL is enabled by one second enable pulse.
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6.发明申请公开(公告)号：US20170345469A1
公开(公告)日：2017-11-30
申请号：US15499876
申请日：2017-04-27
Applicant: MEDIATEK INC.
Inventor： Chi-Hao Hong , Dao-Ping Wang , Yi-Wei Chen , Yi-Ping Kuo , Shu-Lin Lai
Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.
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