公开(公告)号：US11676657B2

公开(公告)日：2023-06-13

申请号：US17210521

申请日：2021-03-24

Applicant: MEDIATEK INC.

Inventor： Yi-Ping Kuo ,  Yi-Te Chiu

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

公开(公告)号：US20210327500A1

公开(公告)日：2021-10-21

申请号：US17210521

申请日：2021-03-24

Applicant: MEDIATEK INC.

Inventor： Yi-Ping Kuo ,  Yi-Te Chiu

IPC: G11C11/419

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

公开(公告)号：US10176853B2

公开(公告)日：2019-01-08

申请号：US15499876

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Chi-Hao Hong ,  Dao-Ping Wang ,  Yi-Wei Chen ,  Yi-Ping Kuo ,  Shu-Lin Lai

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/10 ,  G11C7/08

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.

公开(公告)号：US20240312557A1

公开(公告)日：2024-09-19

申请号：US18443347

申请日：2024-02-16

Applicant: MEDIATEK INC.

Inventor： Che-Wei Chou ,  Ya-Ting Yang ,  Shu-Lin Lai ,  Chi-Kai Hsieh ,  Yi-Ping Kuo ,  Chi-Hao Hong ,  Jia-Jing Chen ,  Yi-Te Chiu ,  Jiann-Tseng Huang

IPC: G11C29/00 ,  G11C29/56

CPC classification number: G11C29/702 ,  G11C29/56008 ,  G11C29/56016

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

公开(公告)号：US20220406373A1

公开(公告)日：2022-12-22

申请号：US17894191

申请日：2022-08-24

Applicant: MEDIATEK INC.

Inventor： Yi-Ping Kuo ,  Yi-Te Chiu

IPC: G11C11/419

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

公开(公告)号：US11887660B2

公开(公告)日：2024-01-30

申请号：US17894191

申请日：2022-08-24

Applicant: MEDIATEK INC.

Inventor： Yi-Ping Kuo ,  Yi-Te Chiu

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

公开(公告)号：US20170345469A1

公开(公告)日：2017-11-30

申请号：US15499876

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Chi-Hao Hong ,  Dao-Ping Wang ,  Yi-Wei Chen ,  Yi-Ping Kuo ,  Shu-Lin Lai

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/109

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.