公开(公告)号：US20240312557A1

公开(公告)日：2024-09-19

申请号：US18443347

申请日：2024-02-16

Applicant: MEDIATEK INC.

Inventor： Che-Wei Chou ,  Ya-Ting Yang ,  Shu-Lin Lai ,  Chi-Kai Hsieh ,  Yi-Ping Kuo ,  Chi-Hao Hong ,  Jia-Jing Chen ,  Yi-Te Chiu ,  Jiann-Tseng Huang

IPC: G11C29/00 ,  G11C29/56

CPC classification number: G11C29/702 ,  G11C29/56008 ,  G11C29/56016

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

公开(公告)号：US20240412779A1

公开(公告)日：2024-12-12

申请号：US18739363

申请日：2024-06-11

Applicant: MEDIATEK INC.

Inventor： Yi-Te Chiu ,  Ya-Ting Yang ,  Jia-Jing Chen

IPC: G11C11/418 ,  G11C5/06

Abstract: A pre-charge system includes a pre-charge circuit and a timing controller circuit. The pre-charge circuit performs time-division pre-charge upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals, wherein the memory array includes a plurality of memory cells each coupled to one of the plurality of bit-line groups. The timing controller circuit generates and outputs the plurality of pre-charge timing control signals to the pre-charge circuit.