公开(公告)号：US20180061786A1

公开(公告)日：2018-03-01

申请号：US15682908

申请日：2017-08-22

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou LIN ,  Chih-Chun HSU ,  Wen-Chou WU

IPC: H01L23/66 ,  H01L25/065 ,  H01L23/64

CPC classification number: H01L23/66 ,  H01L23/552 ,  H01L23/645 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/6605 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06572

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.

公开(公告)号：US20180108624A1

公开(公告)日：2018-04-19

申请号：US15841667

申请日：2017-12-14

Applicant: MEDIATEK INC.

Inventor： Chih-Chun HSU ,  Sheng-Mou LIN

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/31

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3D) antenna. The 3D antenna includes a planar structure portion disposed on the package substrate in the second region, and a bridge structure portion above the planar structure portion and connected thereto.

公开(公告)号：US20230253390A1

公开(公告)日：2023-08-10

申请号：US18154413

申请日：2023-01-13

Applicant: MEDIATEK INC.

Inventor： Ruey-Bo SUN ,  Chih-Chun HSU ,  Sheng-Mou LIN

IPC: H01L25/18 ,  H01L23/552 ,  H01L23/522 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/552 ,  H01L23/5227 ,  H01L23/49822 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/48227 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2224/32145 ,  H01L2224/73265 ,  H01L2224/32225

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a base, a first system-on-chip (SOC) die, a conductive routing and a first shielding film. The first SOC die is disposed on the base. The first SOC die has a front surface and a back surface. The first SOC die includes a first inductor close to the front surface. The conductive routing is disposed on the back surface of the first SOC die. The first shielding film is disposed between the first SOC die and the conductive routing. The first shielding film covers the back surface of the first SOC die and fully overlaps the first inductor.

公开(公告)号：US20170194271A1

公开(公告)日：2017-07-06

申请号：US15335226

申请日：2016-10-26

Applicant: MEDIATEK INC.

Inventor： Chih-Chun HSU ,  Sheng-Mou LIN

IPC: H01L23/66 ,  H01L23/552 ,  H01L23/31

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region. A semiconductor die is disposed on the package substrate in the first region. A three-dimensional (3D) antenna is disposed on the package substrate in the second region. The 3D antenna includes a planar structure portion and a bridge or wall structure portion. A molding compound encapsulates the semiconductor die and at least a portion of the 3D antenna. A conductive shielding element is inside the molding compound or partially covers the molding compound. A semiconductor package assembly having the semiconductor package is also provided.