公开(公告)号：US20240347479A1

公开(公告)日：2024-10-17

申请号：US18611681

申请日：2024-03-20

Applicant: MEDIATEK INC.

Inventor： Chu-Chia Chang ,  Pei-Haw Tsao ,  Peng-Yu Huang ,  Yu-Liang Hsiao ,  Wei-Fan Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/564 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate having a top surface and an opposing bottom surface. The package substrate includes a top build-up wiring layer and an upper dielectric layer covering the top build-up wiring layer. A semiconductor device and a passive component are mounted on the top surface of the package substrate in a side-by-side manner. A molding compound encapsulates the semiconductor device and the passive component on the top surface of the package substrate. A cavity is disposed between the passive component and the top surface of the package substrate. A moisture passing gap is disposed in the top build-up wiring layer of the package substrate

公开(公告)号：US20230134332A1

公开(公告)日：2023-05-04

申请号：US17948195

申请日：2022-09-19

Applicant: MEDIATEK INC.

Inventor： Chu-Chia Chang

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/495 ,  H01L23/14

Abstract: A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.

公开(公告)号：US20220328382A1

公开(公告)日：2022-10-13

申请号：US17706620

申请日：2022-03-29

Applicant: MEDIATEK INC.

Inventor： Chu-Chia Chang ,  Wei-Lun Hsu

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A grid array type lead frame package includes a lead frame having a plurality of bonding fingers projecting inwardly from a periphery of the lead frame; a semiconductor device mounted on inner ends of the bonding fingers, wherein the semiconductor device comprises an active surface and a plurality of input/output (I/O) pads disposed on the active surface; a plurality of bonding wires extending between the I/O pads and the bonding fingers for transmitting signals from or to the semiconductor device; a molding compound at least partially encapsulating the semiconductor device, the bonding wires, and the bonding fingers; and a solder mask layer attached to a bottom surface of the molding compound and a bottom surface of each of the bonding fingers.