公开(公告)号：US20240290737A1

公开(公告)日：2024-08-29

申请号：US18418320

申请日：2024-01-21

Applicant: MEDIATEK INC.

Inventor： Hung-Pin Tsai ,  Pei-Haw Tsao ,  Nai-Wei Liu ,  Wen-Sung Hsu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155

Abstract: A bump structure includes a conductive pad on a semiconductor die; a passivation layer covering a perimeter of the conductive pad; and a first polymer layer on the passivation layer. The first polymer layer includes a via opening partially exposing the central portion of the conductive pad. A RDL is disposed on the first polymer layer and patterned into a bump pad situated directly above the conductive pad. The via opening is completely filled with the RDL and a RDL via is integrally formed with the bump pad. A second polymer layer is disposed on the first polymer layer. An island of the second polymer layer is disposed at a central portion of the bump pad. UBM layer is disposed on the bump pad. The UBM layer covers the island and forms a bulge thereon. A bump is disposed on the UBM layer.

公开(公告)号：US20240178159A1

公开(公告)日：2024-05-30

申请号：US18502105

申请日：2023-11-06

Applicant: MEDIATEK INC.

Inventor： Pei-Haw Tsao ,  Te-Chi Wong

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/49816 ,  H01L24/20 ,  H01L2224/215 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941

Abstract: A coreless substrate package includes a coreless substrate; a package device mounted on a coreless substrate; an underfill material filling into a space between the package device and the coreless substrate; a stiffener ring disposed on a top surface of the coreless substrate along perimeter of the coreless substrate; and a gap fill material disposed in a gap between the stiffener ring and the package device.

公开(公告)号：US20240347479A1

公开(公告)日：2024-10-17

申请号：US18611681

申请日：2024-03-20

Applicant: MEDIATEK INC.

Inventor： Chu-Chia Chang ,  Pei-Haw Tsao ,  Peng-Yu Huang ,  Yu-Liang Hsiao ,  Wei-Fan Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/564 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate having a top surface and an opposing bottom surface. The package substrate includes a top build-up wiring layer and an upper dielectric layer covering the top build-up wiring layer. A semiconductor device and a passive component are mounted on the top surface of the package substrate in a side-by-side manner. A molding compound encapsulates the semiconductor device and the passive component on the top surface of the package substrate. A cavity is disposed between the passive component and the top surface of the package substrate. A moisture passing gap is disposed in the top build-up wiring layer of the package substrate

公开(公告)号：US20230386954A1

公开(公告)日：2023-11-30

申请号：US18132437

申请日：2023-04-10

Applicant: MEDIATEK INC.

Inventor： Yu-Tung Chen ,  Pei-Haw Tsao ,  Kuo-Lung Fan

IPC: H01L23/31 ,  H01L21/683

CPC classification number: H01L23/3185 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68377

Abstract: A wafer level chip scale package includes a bare silicon die having an active surface, a rear surface opposite to the active surface, and a sidewall surface between the active surface and the rear surface. The bare silicon die includes a backside corner between the rear surface and the sidewall surface. A plurality of pads is disposed on the active surface. A plurality of conductive elements is disposed on the plurality of pads, respectively. A backside tape is adhered to the rear surface by using an adhesive layer. The adhesive layer and the backside tape protrude beyond the sidewall surfaces of the bare silicon die. The adhesive layer extends along the sidewall surface and wraps around the backside corner.

公开(公告)号：US20250112166A1

公开(公告)日：2025-04-03

申请号：US18892518

申请日：2024-09-22

Applicant: MEDIATEK INC.

Inventor： Pei-Haw Tsao ,  Te-Chi Wong

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

Abstract: A flip-chip package includes a substrate having a bond pad in a die-mounting area of the substrate. A DRAM die is mounted on the die-mounting area of the substrate in a flip chip fashion. The DRAM die includes an input/output (I/O) pad on its active surface and the I/O pad is electrically coupled to the t bond pad through a connecting element. The bond pad has a diameter that is smaller than a diameter of the I/O pad. A SoC die is mounted on the substrate in a flip chip fashion. The DRAM die and the SoC die are mounted on the substrate in a side-by-side manner.

公开(公告)号：US20240243098A1

公开(公告)日：2024-07-18

申请号：US18542762

申请日：2023-12-17

Applicant: MEDIATEK INC.

Inventor： Pei-Haw Tsao ,  Te-Chi Wong

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/0655 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes a package substrate, an interposer on and electrically connected to the package substrate, a central logic die disposed on and electrically connected to the interposer, peripheral function dies disposed on and electrically connected to the interposer and located in proximity to the central logic die, and at least one dummy die disposed between the central logic die and the peripheral function dies so as to form a rectangular shaped die arrangement. The at least one dummy die is disposed at a corner position of the rectangular shaped die arrangement.