公开(公告)号：US20170272074A1

公开(公告)日：2017-09-21

申请号：US15611822

申请日：2017-06-02

申请人： MediaTek Inc.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H03K19/0175 ,  H03F3/217 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L27/20 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/34 ,  H04L25/08

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US09124267B2

公开(公告)日：2015-09-01

申请号：US14281902

申请日：2014-05-20

申请人： MEDIATEK INC.

发明人： Wen-Chieh Wang ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  I-Wen Liu ,  Khurram Muhammad ,  Chih-Ming Hung

IPC分类号： H04L27/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

摘要翻译： 数字发射机包括：多个可调延迟线，其布置成通过多个延迟时间来延迟多个数字输入信号，以分别产生多个延迟的数字输入信号; 多个转换装置，被配置为分别将多个延迟的数字输入信号转换成多个转换信号; 以及校准装置，其布置成调整多个可调延迟线中的至少一个可调节延迟线的延迟时间，以使多个转换装置在相应的期望时间点转换多个延迟的数字输入信号。

公开(公告)号：US20150102868A1

公开(公告)日：2015-04-16

申请号：US14576152

申请日：2014-12-18

申请人： MEDIATEK INC.

发明人： Robert Bogdan Staszewski ,  Chi-Hsueh Wang

IPC分类号： H03C3/09

CPC分类号： H03C3/0958 ,  H04L27/12 ,  H04L27/127

摘要： A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

摘要翻译： 频率调制器包括数字控制振荡器（DCO），其被配置为响应于调制调谐字和锁相环（PLL）调谐字产生频率偏差。 此外，另一个频率调制器包括DCO和DCO接口电路。 DCO被布置成响应于整数调整字和分数调谐字产生频率偏差。 DCO接口电路用于将整数调整字和分数调谐字产生到DCO，其中分数调谐字通过定点调谐字的异步采样获得。

公开(公告)号：US20140348279A1

公开(公告)日：2014-11-27

申请号：US14273547

申请日：2014-05-09

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

摘要翻译： 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。

公开(公告)号：US09118371B2

公开(公告)日：2015-08-25

申请号：US14281916

申请日：2014-05-20

申请人： MEDIATEK INC.

发明人： Chi-Hsueh Wang ,  Yang-Chuan Chen ,  Hsiang-Hui Chang ,  Li-Shin Lai ,  Khurram Muhammad

IPC分类号： H04K1/02 ,  H04B1/04 ,  H04L25/08 ,  H03F3/217 ,  H03F3/24 ,  H03G3/00

CPC分类号： H04B1/0475 ,  H03F1/02 ,  H03F3/2178 ,  H03F3/24 ,  H03G3/002 ,  H04B2001/045 ,  H04L25/08

摘要： A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

摘要翻译： 数字发射机包括：多个转换装置，被配置为根据多个数字输入信号产生多个转换信号; 补偿装置，被配置为根据所述多个数字输入信号生成至少一个补偿信号; 以及组合电路，被配置为根据所述多个转换信号和所述至少一个补偿信号输出放大的输出信号。

公开(公告)号：US09094004B2

公开(公告)日：2015-07-28

申请号：US14280683

申请日：2014-05-19

申请人： MediaTek Inc.

发明人： Ming-Yu Hsieh ,  Chi-Hsueh Wang ,  Pou-Chi Chang

IPC分类号： H04L25/49 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A transmitter system includes a digital phase rotator, a phase rotation controller, and a digital radio-frequency (RF) transmitter. The digital phase rotator receives a first constellation data, and applies a digital phase rotation to the received first constellation data to generate a second constellation data. The phase rotation controller configures the digital phase rotation. The digital RF transmitter receives a digital input data derived from the second constellation data, and converts the digital input data into an analog RF output.

摘要翻译： 发射机系统包括数字相位旋转器，相位旋转控制器和数字射频（RF）发射器。 数字相位旋转器接收第一星座数据，并且对所接收的第一星座数据应用数字相位旋转以产生第二星座数据。 相位旋转控制器配置数字相位旋转。 数字RF发射器接收从第二星座数据得到的数字输入数据，并将数字输入数据转换为模拟RF输出。

公开(公告)号：US20140348217A1

公开(公告)日：2014-11-27

申请号：US14280683

申请日：2014-05-19

申请人： MEDIATEK INC.

发明人： Ming-Yu Hsieh ,  Chi-Hsueh Wang ,  Pou-Chi Chang

IPC分类号： H04L27/34

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A transmitter system includes a digital phase rotator, a phase rotation controller, and a digital radio-frequency (RF) transmitter. The digital phase rotator receives a first constellation data, and applies a digital phase rotation to the received first constellation data to generate a second constellation data. The phase rotation controller configures the digital phase rotation. The digital RF transmitter receives a digital input data derived from the second constellation data, and converts the digital input data into an analog RF output.

摘要翻译： 发射机系统包括数字相位旋转器，相位旋转控制器和数字射频（RF）发射器。 数字相位旋转器接收第一星座数据，并且对所接收的第一星座数据应用数字相位旋转以产生第二星座数据。 相位旋转控制器配置数字相位旋转。 数字RF发射器接收从第二星座数据得到的数字输入数据，并将数字输入数据转换为模拟RF输出。

公开(公告)号：US10680626B2

公开(公告)日：2020-06-09

申请号：US16120513

申请日：2018-09-04

申请人： MEDIATEK Inc.

发明人： Chieh-Hsun Hsiao ,  Shih-Chi Shen ,  Chi-Hsueh Wang ,  Hsin-Hung Chen

IPC分类号： H03L7/099 ,  G04F10/00 ,  H02M3/07 ,  H03L7/093

摘要： The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.

公开(公告)号：US09577638B2

公开(公告)日：2017-02-21

申请号：US14273547

申请日：2014-05-09

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

摘要翻译： 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。

公开(公告)号：US20160373243A1

公开(公告)日：2016-12-22

申请号：US15255159

申请日：2016-09-02

申请人： MEDIATEK INC.

发明人： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC分类号： H04L7/00

CPC分类号： H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

摘要： A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

摘要翻译： 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。