公开(公告)号：US09830242B2

公开(公告)日：2017-11-28

申请号：US14882416

申请日：2015-10-13

Applicant: MEDIATEK INC.

Inventor： Ran-How Chen ,  Ming-Fang Tsai ,  Chih-Jen Tsai ,  Hsin-Hsien Huang

IPC: G06F9/46 ,  G06F17/00 ,  G06N5/00 ,  G06N5/02 ,  G06F11/30 ,  G06F11/00 ,  G06F9/48

CPC classification number: G06F11/30 ,  G06F9/48 ,  G06F9/4843 ,  G06F11/00 ,  G06F11/3003 ,  G06F11/3006 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3476 ,  G06F2209/508 ,  G06N5/00 ,  G06N5/02 ,  G06N5/022

Abstract: The present invention provides a loading calculation method and a loading calculation system for a processor in an electronic device is disclosed. The loading calculation system comprises: a detecting unit, a determining unit, a generating unit, and a calculating unit. The loading calculation method comprises: detecting a plurality of switching actions of the processor to generate a detecting result; determining a time interval to separate the detecting result to generate a plurality of time periods; generating a log file of scheduling according to the detecting result and the plurality of time periods; utilizing the processor for enabling the log file of scheduling; and calculating the processor loading according to the log file of scheduling.

公开(公告)号：US20230376653A1

公开(公告)日：2023-11-23

申请号：US18315904

申请日：2023-05-11

Applicant: MediaTek Inc.

Inventor： Hsin-Chuan Kuo ,  Chia-Wei Chen ,  Yu-Hsiu Lin ,  Kun-Yu Wang ,  Sheng-Tai Tseng ,  Chun-Ku Ting ,  Fang-Ming Yang ,  Yu-Hsien Ku ,  Jen-Wei Lee ,  Ronald Kuo-Hua Ho ,  Chun-Chieh Wang ,  Yi-Ying Liao ,  Tai-Lai Tung ,  Ming-Fang Tsai ,  Chun-Chih Yang ,  Chih-Wei Ko ,  Kun-Chin Huang

IPC: G06F30/27 ,  G06F30/392

CPC classification number: G06F30/27 ,  G06F30/392

Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.

公开(公告)号：US20230376671A1

公开(公告)日：2023-11-23

申请号：US18315712

申请日：2023-05-11

Applicant: MediaTek Inc.

Inventor： Jen-Wei Lee ,  Yi-Ying Liao ,  Te-Wei Chen ,  Yu-Hsiu Lin ,  Chia-Wei Chen ,  Chun-Ku Ting ,  Sheng-Tai Tseng ,  Ronald Kuo-Hua Ho ,  Hsin-Chuan Kuo ,  Chun-Chieh Wang ,  Ming-Fang Tsai ,  Chun-Chih Yang ,  Tai-Lai Tung ,  Da-Shan Shiu

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/20

Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.

公开(公告)号：US20160203020A1

公开(公告)日：2016-07-14

申请号：US14882416

申请日：2015-10-13

Applicant: MEDIATEK INC.

Inventor： Ran-How Chen ,  Ming-Fang Tsai ,  Chih-Jen Tsai ,  Hsin-Hsien Huang

IPC: G06F9/48

CPC classification number: G06F11/30 ,  G06F9/48 ,  G06F9/4843 ,  G06F11/00 ,  G06F11/3003 ,  G06F11/3006 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3476 ,  G06F2209/508 ,  G06N5/00 ,  G06N5/02 ,  G06N5/022

Abstract: The present invention provides a loading calculation method and a loading calculation system for a processor in an electronic device is disclosed. The loading calculation system comprises: a detecting unit, a determining unit, a generating unit, and a calculating unit. The loading calculation method comprises: detecting a plurality of switching actions of the processor to generate a detecting result; determining a time interval to separate the detecting result to generate a plurality of time periods; generating a log file of scheduling according to the detecting result and the plurality of time periods; utilizing the processor for enabling the log file of scheduling; and calculating the processor loading according to the log file of scheduling.

Abstract translation: 本发明提供了一种用于电子设备中的处理器的加载计算方法和加载计算系统。 加载计算系统包括：检测单元，确定单元，生成单元和计算单元。 加载计算方法包括：检测处理器的多个切换动作以产生检测结果; 确定分离检测结果以产生多个时间段的时间间隔; 根据检测结果和多个时间段生成调度日志文件; 利用处理器来启用调度的日志文件; 并根据调度的日志文件计算处理器负载。