公开(公告)号：US20160342198A1

公开(公告)日：2016-11-24

申请号：US14845879

申请日：2015-09-04

Applicant: MediaTek Inc.

Inventor： Jih-Ming HSU ,  Yen-Lin LEE ,  Jia-Ming CHEN ,  Shih-Yen CHIU ,  Chung-Ho CHANG ,  Ya-Ting CHANG ,  Ming-Hsien LEE

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

Abstract translation: 计算系统包括多核处理器和核心控制器。 核心控制器用于：监控多核处理器的利用率; 根据多核处理器的利用率，目标利用率和第一性能指标来计算目标性能指标，其中所述第一性能指标与动态电压频率缩放（DVFS）表的第一项相关联，所述动态电压频率缩放（DVFS）表对应于 多核处理器的当前设置; 以及根据所述目标性能指标和与所述第二条目相关联的第二性能指标来选择对应于目标设置的所述DVFS表的第二条目。 目标设置用于配置多核处理器。

公开(公告)号：US20160327999A1

公开(公告)日：2016-11-10

申请号：US15107984

申请日：2015-09-17

Applicant: MEDIATEK INC.

Inventor： Ya-Ting CHANG ,  Lee-Kee YONG ,  Shih-Yen CHIU ,  Ming-Hsien LEE ,  Jia-Ming CHEN ,  Yu-Ming LIN ,  Hung-Lin CHOU ,  Tzu-Jen LO ,  Koon Woon SOON

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/20 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A computing system with multiple processor cores manages power and performance by dynamic frequency scaling. The system detects a condition when a total number of active processor cores within one or more clusters is less than a predetermined number, and an operating frequency of the active processor cores has risen to a specified highest frequency. The system also obtains ambient temperature measurement of the one or more clusters. Upon detecting the condition, the system increases the operating frequency above the specified highest frequency based on the ambient temperature measurement while maintaining a same level of supply voltage to the active processor cores.

Abstract translation: 具有多个处理器内核的计算系统通过动态频率缩放来管理功耗和性能。 当一个或多个集群内的活动处理器核心总数小于预定数量时，系统检测到状态，并且活动处理器核心的工作频率已经升高到指定的最高频率。 该系统还获得一个或多个簇的环境温度测量。 在检测到状况时，系统会根据环境温度测量值将工作频率提高到高于规定的最高频率，同时保持与主动处理器内核相同的电源电压。

公开(公告)号：US20160139964A1

公开(公告)日：2016-05-19

申请号：US14936686

申请日：2015-11-10

Applicant: MediaTek Inc.

Inventor： Jia-Ming CHEN ,  Hung-Lin CHOU ,  Ya-Ting CHANG ,  Shih-Yen CHIU ,  Chia-Hao HSU ,  Yu-Ming LIN ,  Wan-Ching HUANG ,  Jen-Chieh YANG ,  Pi-Cheng HSIAO

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/329 ,  G06F2209/505 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

Abstract translation: 具有不同能量效率特性的处理器核心的多集群系统被配置为以高效率运行，从而可以满足性能和功率要求。 该系统包括组中层次结构中的多个处理器核心。 组的层次结构包括：多个一级组，每个一级组，包括具有相同能量效率特性的一个或多个处理器核心，以及被配置为由一级调度器分配任务的每个一级组; 一个或多个2级组，每个2级组包括相应的1级组，具有不同能量效率特性的相同2级组的不同级别1组中的处理器核心，以及被配置为 由相应的二级调度程序分配任务; 以及包括一个或多个2级组并被配置为由3级调度器分配任务的3级组。