公开(公告)号：US20210044301A1

公开(公告)日：2021-02-11

申请号：US16934002

申请日：2020-07-20

Applicant: MEDIATEK INC.

Inventor： Chan-Hsiang Weng ,  Hung-Yi Hsieh ,  Tzu-An Wei ,  Ting-Yang Wang

IPC: H03M1/80 ,  H03M1/08 ,  H03M1/12 ,  H03M1/06 ,  H03M1/38

Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.

公开(公告)号：US11121720B2

公开(公告)日：2021-09-14

申请号：US16934002

申请日：2020-07-20

Applicant: MEDIATEK INC.

Inventor： Chan-Hsiang Weng ,  Hung-Yi Hsieh ,  Tzu-An Wei ,  Ting-Yang Wang

IPC: H03M1/80 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M1/38

Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.

公开(公告)号：US10944418B2

公开(公告)日：2021-03-09

申请号：US16188217

申请日：2018-11-12

Applicant: MEDIATEK INC.

Inventor： Ting-Yang Wang ,  Hung-Yi Hsieh ,  Tzu-An Wei ,  Tien-Yu Lo

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/38

Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

公开(公告)号：US20190238151A1

公开(公告)日：2019-08-01

申请号：US16188217

申请日：2018-11-12

Applicant: MEDIATEK INC.

Inventor： Ting-Yang Wang ,  Hung-Yi Hsieh ,  Tzu-An Wei ,  Tien-Yu Lo

IPC: H03M3/00

CPC classification number: H03M3/32 ,  H03M1/007 ,  H03M1/38 ,  H03M3/30 ,  H03M3/426 ,  H03M3/436 ,  H03M3/464

Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.