公开(公告)号：US20140103433A1

公开(公告)日：2014-04-17

申请号：US14140544

申请日：2013-12-26

Applicant: MEDIATEK INC.

Inventor： Ming-Cheng Lee ,  Wei-Li Tsao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42372 ,  H01L29/4983

Abstract: A high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region.

Abstract translation: 高压金属电介质半导体晶体管包括半导体衬底; 围绕有源区的半导体衬底中的沟槽隔离区; 一个覆盖活跃区域的门; 在有源区中的第一导电类型的漏极掺杂区; 在有源区域中的第二导电类型的第一阱中的第一导电类型的源极掺杂区域; 以及在栅极和源极掺杂区域之间的第一导电类型的源极轻掺杂区域; 其中在栅极和漏极掺杂区域之间不形成隔离。

公开(公告)号：US20130105899A1

公开(公告)日：2013-05-02

申请号：US13719249

申请日：2012-12-19

Applicant: MEDIATEK INC.

Inventor： Tung-Hsing Lee ,  I-Cheng Lin ,  Wei-Li Tsao

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823418 ,  H01L27/0266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region. The I/O ESD device has an asymmetric LDD configuration. In one embodiment, a junction of the second LDD region is shallower than that of the first LDD region.

Abstract translation: 一种在衬底上具有栅电极的I / O静电放电（ESD）器件，在栅电极和衬底之间的栅极电介质层，分别设置在栅电极的两个相对侧壁上的一对侧壁间隔物，第一轻掺杂 漏极（LDD）区域，设置在第一LDD区域旁边的源极区域，设置在另一侧壁间隔物下方的第二LDD区域和设置在第二LDD区域附近的漏极区域。 I / O ESD器件具有非对称LDD配置。 在一个实施例中，第二LDD区域的结点比第一LDD区域的结浅。