公开(公告)号：US09747963B2

公开(公告)日：2017-08-29

申请号：US14530837

申请日：2014-11-03

Applicant: MEDIATEK INC.

Inventor： Ming-Hsien Lee ,  Yun-Ching Li ,  Yi-Chih Huang ,  Chun-Fang Peng

IPC: G06F3/00 ,  G11C8/18 ,  G11C5/14 ,  G11C8/06 ,  G11C8/08 ,  G06F13/16 ,  G11C7/10 ,  G06F12/06

CPC classification number: G11C8/18 ,  G06F12/0607 ,  G06F13/1684 ,  G06F13/1689 ,  G11C5/14 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.

公开(公告)号：US20160125923A1

公开(公告)日：2016-05-05

申请号：US14530837

申请日：2014-11-03

Applicant: MEDIATEK INC.

Inventor： Ming-Hsien Lee ,  Yun-Ching Li ,  Yi-Chih Huang ,  Chun-Fang Peng

IPC: G11C8/18 ,  G11C8/08 ,  G11C8/06 ,  G06F12/02 ,  G11C5/14

CPC classification number: G11C8/18 ,  G06F12/0607 ,  G06F13/1684 ,  G06F13/1689 ,  G11C5/14 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.

Abstract translation: 多通道存储器系统具有存储器件，多个通道和控制电路。 存储装置具有多个存储器存储空间。 通道分别耦合到存储器存储空间，其中每个通道被配置为用作独立地访问对应的存储器存储空间的存储器接口。 控制电路分别控制通道上时钟的时钟频率。 在同一时间点，信道至少包括以由控制电路设置的第一时钟频率操作的第一信道和在同一时间点由控制电路设置的第二时钟频率操作的第二信道，以及第二时钟 频率与第一个时钟频率不同。