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公开(公告)号：US11996598B2
公开(公告)日：2024-05-28
申请号：US18079847
申请日：2022-12-12
Applicant: MEDIATEK INC.
Inventor： Li Gao , Zhiming Deng
IPC: H01P1/00
CPC classification number: H01P1/00
Abstract: An electronic device and a method for reducing power consumption of signal transmission in the electronic device are provided. The electronic device may include a source circuit, a destination circuit, at least one transmission wire and at least one resonance wire, wherein the at least one transmission wire is coupled between at least one output terminal of the source circuit and at least one input terminal of the destination circuit, and the at least one resonance wire is coupled to the at least one input terminal of the destination circuit and is routed along the at least one transmission wire. In specific, the source circuit is configured to output an oscillation signal having an oscillation frequency, the destination circuit is configured to receive the oscillation signal, wherein the at least one transmission wire is configured to transmit the oscillation signal from the source circuit to the destination circuit.
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公开(公告)号：US20250070894A1
公开(公告)日：2025-02-27
申请号：US18808063
申请日：2024-08-18
Applicant: MEDIATEK INC.
Inventor： Ming-Chou Wu , Edmund, Wen Jen Leong , Chiyuan Lu , Ting-Che Tseng , Zhiming Deng
IPC: H04B17/14
Abstract: A calibration apparatus for calibrating a transceiver includes a loop back circuit, an estimation circuit, and a calibration circuit. The loop back circuit is coupled between a mixer output port of a transmitter (Tx) of the transceiver and a mixer input port of a receiver (Rx) of the transceiver, and applies a sequence of different loop gains. The estimation circuit receives a loop back receiving signal that is output from the Rx under the sequence of different loop gains, and generates at least one estimated value of impairment of the transceiver by performing channel estimation according to at least the loop back receiving signal. The calibration circuit performs calibration upon the transceiver according to the at least one estimated value.
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Patent Agency Ranking
3.发明公开公开(公告)号：US20230299449A1
公开(公告)日：2023-09-21
申请号：US18079847
申请日：2022-12-12
Applicant: MEDIATEK INC.
Inventor： Li Gao , Zhiming Deng
IPC: H01P1/00
CPC classification number: H01P1/00
Abstract: An electronic device and a method for reducing power consumption of signal transmission in the electronic device are provided. The electronic device may include a source circuit, a destination circuit, at least one transmission wire and at least one resonance wire, wherein the at least one transmission wire is coupled between at least one output terminal of the source circuit and at least one input terminal of the destination circuit, and the at least one resonance wire is coupled to the at least one input terminal of the destination circuit and is routed along the at least one transmission wire. In specific, the source circuit is configured to output an oscillation signal having an oscillation frequency, the destination circuit is configured to receive the oscillation signal, wherein the at least one transmission wire is configured to transmit the oscillation signal from the source circuit to the destination circuit.
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公开(公告)号：US20230412136A1
公开(公告)日：2023-12-21
申请号：US18086600
申请日：2022-12-21
Applicant: MEDIATEK INC.
Inventor： Zhiming Deng , Qian Zhong , Li Gao
CPC classification number: H03G5/165 , H03G3/30 , H03G2201/103
Abstract: A gain equalizer and a method for controlling a tunable gain of the gain equalizer are provided. The gain equalizer includes a common source stage and a switch array. The common source stage is configured to apply the tunable gain to an input signal, in order to generate an amplified signal. The common source stage includes input transistors and cascode transistors, wherein the cascode transistors are respectively coupled to the input transistors. The input transistors are configured to receive the input signal via gate terminals of the input transistors, respectively, and the cascode transistors are configured to output the amplified signal via drain terminals of the cascode transistors, respectively. In addition, the switch array is coupled between respective source terminals of the cascode transistors, wherein the tunable gain is controlled according to an equivalent impedance of the switch array.
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5.发明公开公开(公告)号：US20230318556A1
公开(公告)日：2023-10-05
申请号：US18122693
申请日：2023-03-16
Applicant: MEDIATEK INC.
Inventor： Zhiming Deng , Li Gao
CPC classification number: H03G3/3026 , H03F3/2178 , H03F1/0244 , H03F2200/294
Abstract: A variable gain low noise amplifier (LNA) and a method for controlling a gain of the variable gain LNA are provided. The variable gain LNA may include a first transistor, a first degeneration inductor, a second transistor and a second degeneration inductor, wherein the first degeneration inductor is coupled to a source terminal of the first transistor, and the second degeneration inductor is coupled to a source terminal of the second transistor. Gate terminals of the first transistor and the second transistor are configured to receive an input signal. The first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA. More particularly, a gain of the variable gain LNA is determined by controlling whether to turn off the second branch.
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公开(公告)号：US09473195B2
公开(公告)日：2016-10-18
申请号：US14741473
申请日：2015-06-17
Applicant: MEDIATEK INC.
Inventor： Jing-Hong Conan Zhan , Chuan-Kang Liang , Ti-Ku Yu , Zhiming Deng
CPC classification number: H04B1/40 , H01Q3/30 , H01Q21/0025 , H03F3/19 , H03F3/21 , H03F2200/294 , H03F2200/451 , H04B1/44
Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first transceiving path between one of the plurality of transceiving elements and the signal processing block and a second transceiving path between another of the plurality of transceiving elements and the signal processing block share at least partial signal traces of the first distributed network.
Abstract translation: 相控阵收发器包括：多个天线; 分别耦合到所述多个天线的多个收发元件; 信号处理块; 以及耦合在所述信号处理块和所述收发元件之间的第一分布式网络，其中所述收发元件，所述信号处理块和所述第一分布式网络被配置为单个芯片，以及第一收发路径， 所述信号处理块和所述多个收发元件中的另一个之间的第二收发路径与所述信号处理块共享所述第一分布式网络的至少部分信号迹线。
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公开(公告)号：US20150288411A1
公开(公告)日：2015-10-08
申请号：US14741473
申请日：2015-06-17
Applicant: MEDIATEK INC.
Inventor： Jing-Hong Conan Zhan , Chuan-Kang Liang , Ti-Ku Yu , Zhiming Deng
CPC classification number: H04B1/40 , H01Q3/30 , H01Q21/0025 , H03F3/19 , H03F3/21 , H03F2200/294 , H03F2200/451 , H04B1/44
Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first transceiving path between one of the plurality of transceiving elements and the signal processing block and a second transceiving path between another of the plurality of transceiving elements and the signal processing block share at least partial signal traces of the first distributed network.
Abstract translation: 相控阵收发器包括：多个天线; 分别耦合到所述多个天线的多个收发元件; 信号处理块; 以及耦合在所述信号处理块和所述收发元件之间的第一分布式网络，其中所述收发元件，所述信号处理块和所述第一分布式网络被配置为单个芯片，以及第一收发路径， 所述信号处理块和所述多个收发元件中的另一个之间的第二收发路径与所述信号处理块共享所述第一分布式网络的至少部分信号迹线。
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