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公开(公告)号：US20220200859A1
公开(公告)日：2022-06-23
申请号：US17129978
申请日：2020-12-22
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ido Gilboa , Shay Aisman , Sagi Arieli , Oren Vaserberger , Amit Mandelbaum , Doron Haritan Kazakov , Natali Shechtman , Iftah Levi , Amir Ancel
IPC: H04L12/24 , H04L12/841
Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.
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公开(公告)号：US11757614B2
公开(公告)日：2023-09-12
申请号：US17315396
申请日：2021-05-10
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Natan Manevich , Teferet Geula , Amit Mandelbaum , Ariel Almog
IPC: H04L7/00 , G06N20/00 , H04L43/106
CPC classification number: H04L7/0054 , G06N20/00 , H04L43/106
Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.
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公开(公告)号：US11968089B2
公开(公告)日：2024-04-23
申请号：US17981516
申请日：2022-11-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ido Gilboa , Shay Aisman , Sagi Arieli , Oren Vaserberger , Amit Mandelbaum , Doron Haritan Kazakov , Natali Shechtman , Iftah Levi , Amir Ancel
IPC: H04L41/0823 , H04L41/08 , H04L41/083 , H04L41/085 , H04L41/0866 , H04L47/283
CPC classification number: H04L41/0836 , H04L41/083 , H04L41/085 , H04L41/0866 , H04L41/0886 , H04L47/283
Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.
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公开(公告)号：US11546216B2
公开(公告)日：2023-01-03
申请号：US17129978
申请日：2020-12-22
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ido Gilboa , Shay Aisman , Sagi Arieli , Oren Vaserberger , Amit Mandelbaum , Doron Haritan Kazakov , Natali Shechtman , Iftah Levi , Amir Ancel
IPC: H04L41/0823 , H04L41/083 , H04L47/283 , H04L41/0866 , H04L41/08 , H04L41/085
Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.
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Patent Agency Ranking
公开(公告)号：US20220360423A1
公开(公告)日：2022-11-10
申请号：US17315396
申请日：2021-05-10
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Natan Manevich , Teferet Geula , Amit Mandelbaum , Ariel Almog
Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.
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公开(公告)号：US20220352998A1
公开(公告)日：2022-11-03
申请号：US17246730
申请日：2021-05-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Natan Manevich , Roee Moyal , Eliel Peretz , Eran Ben Elisha , Ariel Almog , Teferet Geula , Amit Mandelbaum
Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.
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公开(公告)号：US20230275906A1
公开(公告)日：2023-08-31
申请号：US17682209
申请日：2022-02-28
Applicant: Mellanox Technologies Ltd.
Inventor： Ohad ZOHAR , Dotan Finkelshtein , Ariel Almog , Nir Getter , Amit Mandelbaum
CPC classification number: H04L63/1416 , H04L63/1425 , H04L63/1466 , G06N20/00 , G06F9/45558 , G06F2009/45595 , G06F2009/45587
Abstract: A method of determining if a virtual machine is executing a network attack may include using a computing device operating a processor: receiving a plurality of jobs from a plurality of virtual machines being executed across time slices on a host computer in a computer network; executing the plurality of jobs using the processor; receiving data from hardware counters of the processor; and based on the data, determining whether or not a virtual machine of the plurality of virtual machines is executing a network attack.
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公开(公告)号：US11641245B2
公开(公告)日：2023-05-02
申请号：US17246730
申请日：2021-05-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Natan Manevich , Roee Moyal , Eliel Peretz , Eran Ben Elisha , Ariel Almog , Teferet Geula , Amit Mandelbaum
IPC: H04J3/06 , H04L43/0817 , H04L43/0882 , H04L67/55
Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.
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公开(公告)号：US20230054873A1
公开(公告)日：2023-02-23
申请号：US17981516
申请日：2022-11-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ido Gilboa , Shay Aisman , Sagi Arieli , Oren Vaserberger , Amit Mandelbaum , Doron Haritan Kazakov , Natali Shechtman , Iftah Levi , Amir Ancel
IPC: H04L41/0823 , H04L41/083 , H04L47/283 , H04L41/0866 , H04L41/08 , H04L41/085
Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.
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