公开(公告)号：US12094522B2

公开(公告)日：2024-09-17

申请号：US17936785

申请日：2022-09-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akeno Ito ,  Mamoru Nishizaki

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4096

Abstract: An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.

公开(公告)号：US11715522B2

公开(公告)日：2023-08-01

申请号：US17359268

申请日：2021-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akeno Ito ,  Takayori Hamada ,  Mamoru Nishizaki

IPC: G11C16/08 ,  G11C16/30 ,  H10B12/00

CPC classification number: G11C16/08 ,  G11C16/30 ,  H10B12/50

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

公开(公告)号：US20220415397A1

公开(公告)日：2022-12-29

申请号：US17359268

申请日：2021-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akeno Ito ,  Takayori Hamada ,  Mamoru Nishizaki

IPC: G11C16/08 ,  G11C16/30 ,  H01L27/108

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.