公开(公告)号：US20130242685A1

公开(公告)日：2013-09-19

申请号：US13886096

申请日：2013-05-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ben Ba ,  Victor Wong

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

Abstract: The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle.

Abstract translation: 这里描述的实施例提供存储器件。 在一个实施例中，存储器设备包括：组控制逻辑，其被配置为生成修改的存储体地址信号;以及主动驱动器，其被配置为提供存储体激活信号，接收激活命令信号，执行激活命令信号的激活命令 一组时钟周期，其中该组时钟周期中的每一个大于一个时钟周期，并且接收修改的库地址信号，其中修改的库地址信号对于每个时钟周期的每一个的至少一部分 一组时钟周期，并且该组时钟周期中的每一个的至少一部分大于一个时钟周期。

公开(公告)号：US08755247B2

公开(公告)日：2014-06-17

申请号：US13886096

申请日：2013-05-02

Applicant: Micron Technology, Inc.

Inventor： Ben Ba ,  Victor Wong

IPC: G11C11/00

CPC classification number: G11C8/08 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

Abstract: The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle.

Abstract translation: 这里描述的实施例提供存储器件。 在一个实施例中，存储器设备包括：组控制逻辑，其被配置为生成修改的存储体地址信号;以及主动驱动器，其被配置为提供存储体激活信号，接收激活命令信号，执行激活命令信号的激活命令 一组时钟周期，其中该组时钟周期中的每一个大于一个时钟周期，并且接收修改的库地址信号，其中修改的库地址信号对于每个时钟周期的每一个的至少一部分 一组时钟周期，并且该组时钟周期中的每一个的至少一部分大于一个时钟周期。