公开(公告)号：US20250130718A1

公开(公告)日：2025-04-24

申请号：US18889047

申请日：2024-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Antonino Caprì ,  Graziano Mirichigni ,  Marco Sforzin ,  Bryan David Kerstetter ,  John David Porter

IPC: G06F3/06

Abstract: A system performs operations including: storing a first value in a first memory location used for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing a second value in a second memory location, wherein the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location comprises a preset value corresponding to a first component of the plurality of components of the memory device; and executing, by the first component, the command.

公开(公告)号：US20230359361A1

公开(公告)日：2023-11-09

申请号：US17662187

申请日：2022-05-05

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald Martin Morgan

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.

公开(公告)号：US20250028449A1

公开(公告)日：2025-01-23

申请号：US18806275

申请日：2024-08-15

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald Martin Morgan

IPC: G06F3/06

Abstract: Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.

公开(公告)号：US20230350574A1

公开(公告)日：2023-11-02

申请号：US17731100

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F3/0676

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

公开(公告)号：US20250085867A1

公开(公告)日：2025-03-13

申请号：US18955719

申请日：2024-11-21

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

IPC: G06F3/06

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

公开(公告)号：US20250044957A1

公开(公告)日：2025-02-06

申请号：US18804609

申请日：2024-08-14

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

公开(公告)号：US12159039B2

公开(公告)日：2024-12-03

申请号：US17731100

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

IPC: G06F3/06

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

公开(公告)号：US12086425B2

公开(公告)日：2024-09-10

申请号：US17730755

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald Martin Morgan ,  Alan J. Wilson

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.

公开(公告)号：US20240231635A1

公开(公告)日：2024-07-11

申请号：US18405998

申请日：2024-01-05

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Bryan David Kerstetter

IPC: G06F3/06 ,  G06F21/56

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/566 ,  G06F2221/034

Abstract: A system for providing maximum row active time enforcement for memory devices is disclosed. A host device issues an activate command to activate a memory bank of a plurality of memory banks of a memory. The memory device activates the memory bank and determines whether a precharge command to close the first memory bank has been issued by the host device within a maximum threshold amount of time since issuance of the activate command. If the system determines that the precharge command has been issued by the host device within the threshold, the memory device closes the memory bank via the host-issued precharge command. If, however, the system determines that the precharge command has not been issued by the host device within the threshold, the memory device internally issues a precharge command to close the memory bank to reduce potential data loss and other harmful effects to the memory device.

公开(公告)号：US20240126476A1

公开(公告)日：2024-04-18

申请号：US17965584

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Bryan David Kerstetter ,  Kwang-Ho Cho

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673

Abstract: A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.